diff -rpuN a/drivers/media/common/tuners/r848.c b/drivers/media/common/tuners/r848.c
--- a/drivers/media/common/tuners/r848.c	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/common/tuners/r848.c	2016-04-09 10:31:21.248007861 -0300
@@ -0,0 +1,4761 @@
+/*
+ * Rafael Micro R848 silicon tuner driver
+ *
+ * Copyright (C) 2015 Luis Alves <ljalvs@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License along
+ *    with this program; if not, write to the Free Software Foundation, Inc.,
+ *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/bitrev.h>
+#include "r848.h"
+#include "r848_priv.h"
+
+/* read multiple (continuous) registers starting at addr */
+static int r848_rdm(struct r848_priv *priv, u8 addr, u8 *buf, int len)
+{
+	int ret, i;
+	struct i2c_msg msg[] = {
+		{ .addr = priv->cfg->i2c_address, .flags = 0,
+			.buf = &addr, .len = 1 },
+		{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
+			.buf = buf, .len = len }
+	};
+
+	ret = i2c_transfer(priv->i2c, msg, 2);
+	if (ret == 2) {
+		for (i = 0; i < len; i++)
+			buf[i] = bitrev8(buf[i]);
+		ret = 0;
+	} else {
+		dev_warn(&priv->i2c->dev, "%s: i2c tuner rd failed=%d " \
+				"len=%d\n", KBUILD_MODNAME, ret, len);
+		ret = -EREMOTEIO;
+	}
+	return ret;
+}
+
+/* write multiple (continuous) registers */
+static int r848_wrm(struct r848_priv *priv, u8 *buf, int len)
+{
+	int ret;
+	struct i2c_msg msg ={
+		.addr = priv->cfg->i2c_address,
+		.flags = 0, .buf = buf, .len = len };
+
+	ret = i2c_transfer(priv->i2c, &msg, 1);
+	if (ret == 1) {
+		ret = 0;
+	} else {
+		dev_warn(&priv->i2c->dev, "%s: i2c tuner wr failed=%d " \
+				"len=%d\n", KBUILD_MODNAME, ret, len);
+		ret = -EREMOTEIO;
+	}
+	return ret;
+}
+
+/* write one register */
+static int r848_wr(struct r848_priv *priv, u8 addr, u8 data)
+{
+	u8 buf[] = { addr, data };
+	return r848_wrm(priv, buf, 2);
+}
+
+/* read one register */
+static int r848_rd(struct r848_priv *priv, u8 addr, u8 *data)
+{
+	return r848_rdm(priv, addr, data, 1);
+}
+
+/* read register, apply masks, write back */
+static int r848_regmask(struct r848_priv *priv,
+	u8 reg, u8 setmask, u8 clrmask)
+{
+	int ret;
+	u8 b = 0;
+	if (clrmask != 0xff) {
+		ret = r848_rd(priv, reg, &b);
+		if (ret)
+			return ret;
+		b &= ~clrmask;
+	}
+	return r848_wr(priv, reg, b | setmask);
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+static int r848_get_lock_status(struct r848_priv *priv, u8 *lock)
+{
+	int ret;
+	u8 buf[3];
+
+	ret = r848_rdm(priv, 0x00, buf, 3);
+	if (ret)
+		return ret;
+	
+	if ((buf[2] & 0x40) == 0x00)
+		*lock = 0;
+	else
+	  	*lock = 1;
+
+	return ret;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+//-----------------------------------------------------------------------------------/ 
+// Purpose: read multiple IMC results for stability
+// input: IMR_Reg: IMC result address
+//        IMR_Result_Data: result 
+// output: TRUE or FALSE
+//-----------------------------------------------------------------------------------/
+static int R848_Muti_Read( struct r848_priv *priv,u8* IMR_Result_Data)
+{
+	u8 ReadCunt     = 0;
+	u16 ReadAmount  = 0;
+	u8 ReadMax = 0;
+	u8 ReadMin = 255;
+	u8 ReadData = 0;
+	I2C_LEN_TYPE R848_I2C_Len;
+
+	u8 buf[2];
+	int ret;
+
+
+    msleep(3);//3
+
+	for(ReadCunt = 0; ReadCunt < 3; ReadCunt ++) {
+#if 0
+		R848_I2C_Len.RegAddr = 0x00;
+		R848_I2C_Len.Len = 2;              // read 0x01
+		if(I2C_Read_Len(priv,&R848_I2C_Len) != RT_Success)
+		{
+			I2C_Read_Len(priv,&R848_I2C_Len);
+		}
+#endif
+		ret = r848_rdm(priv, 0x00, buf, 2);
+		ReadData = (buf[1] & 0x3f);
+		
+		ReadAmount = ReadAmount + (u16)ReadData;
+		
+		if(ReadData < ReadMin)
+			ReadMin = ReadData;
+		
+        if(ReadData > ReadMax)
+			ReadMax = ReadData;
+	}
+	*IMR_Result_Data = (u8) (ReadAmount - (u16)ReadMax - (u16)ReadMin);
+
+
+	return RT_Success;
+}
+
+R848_Freq_Info_Type R848_Freq_Sel(u32 LO_freq, u32 RF_freq,R848_Standard_Type R848_Standard)
+{
+	R848_Freq_Info_Type R848_Freq_Info;
+
+	//----- RF dependent parameter --------????
+	//LNA band  R13[6:5]
+	if(RF_freq<R848_LNA_LOW_LOWEST[R848_TF_BEAD])  //<164
+		 R848_Freq_Info.LNA_BAND = 0x60;   // ultra low			// R848:R13[6:5]
+	else if((RF_freq>=R848_LNA_LOW_LOWEST[R848_TF_BEAD]) && (RF_freq<
+R848_LNA_MID_LOW[R848_TF_BEAD]))  //164~388
+		 R848_Freq_Info.LNA_BAND = 0x40;   //low					// R848:R13[6:5]
+	else if((RF_freq>=R848_LNA_MID_LOW[R848_TF_BEAD]) && (RF_freq<
+R848_LNA_HIGH_MID[R848_TF_BEAD]))  //388~612
+		 R848_Freq_Info.LNA_BAND = 0x20;   // mid					// R848:R13[6:5]
+	else     // >612
+		 R848_Freq_Info.LNA_BAND = 0x00;   // high				// R848:R13[6:5]
+	
+	//----- LO dependent parameter --------
+	//IMR point 
+	if(LO_freq<133000)  
+         R848_Freq_Info.IMR_MEM = 0;   
+	else if((LO_freq>=133000) && (LO_freq<221000))  
+         R848_Freq_Info.IMR_MEM = 1;   
+	else if((LO_freq>=221000) && (LO_freq<450000))  
+		 R848_Freq_Info.IMR_MEM = 2;  
+	else if((LO_freq>=450000) && (LO_freq<775000))  
+		 R848_Freq_Info.IMR_MEM = 3; 
+	else 
+		 R848_Freq_Info.IMR_MEM = 4; 
+
+	//RF polyfilter band   R33[7:6]
+	if(LO_freq<133000)  
+         R848_Freq_Info.RF_POLY = 0x80;   //low	
+	else if((LO_freq>=133000) && (LO_freq<221000))  
+         R848_Freq_Info.RF_POLY = 0x40;   // mid
+	else if((LO_freq>=221000) && (LO_freq<775000))  
+		 R848_Freq_Info.RF_POLY = 0x00;   // highest
+	else
+		 R848_Freq_Info.RF_POLY = 0xC0;   // ultra high
+
+	
+	//LPF Cap, Notch
+	switch(R848_Standard)
+	{
+		case R848_DVB_C_8M:
+		case R848_DVB_C_6M:
+		case R848_J83B:
+        case R848_DVB_C_8M_IF_5M:
+		case R848_DVB_C_6M_IF_5M:
+		case R848_J83B_IF_5M:
+			if( LO_freq<77000)  
+			{
+				R848_Freq_Info.LPF_CAP = 16;
+				R848_Freq_Info.LPF_NOTCH = 10;
+			}
+			else if((LO_freq>=77000) && (LO_freq<85000))
+			{
+				R848_Freq_Info.LPF_CAP = 16;
+				R848_Freq_Info.LPF_NOTCH = 4;
+			}
+			else if((LO_freq>=85000) && (LO_freq<115000))
+			{
+				R848_Freq_Info.LPF_CAP = 13;
+				R848_Freq_Info.LPF_NOTCH = 3;
+			}
+			else if((LO_freq>=115000) && (LO_freq<125000))
+			{
+				R848_Freq_Info.LPF_CAP = 11;
+				R848_Freq_Info.LPF_NOTCH = 1;
+			}
+			else if((LO_freq>=125000) && (LO_freq<141000))
+			{
+				R848_Freq_Info.LPF_CAP = 9;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else if((LO_freq>=141000) && (LO_freq<157000))
+			{
+				R848_Freq_Info.LPF_CAP = 8;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else if((LO_freq>=157000) && (LO_freq<181000))
+			{
+				R848_Freq_Info.LPF_CAP = 6;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else if((LO_freq>=181000) && (LO_freq<205000))
+			{
+				R848_Freq_Info.LPF_CAP = 3;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else //LO>=201M
+			{
+				R848_Freq_Info.LPF_CAP = 0;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+
+			break;
+
+		default:
+			if(LO_freq<73000)  
+			{
+				R848_Freq_Info.LPF_CAP = 8;
+				R848_Freq_Info.LPF_NOTCH = 10;
+			}
+			else if((LO_freq>=73000) && (LO_freq<81000))
+			{
+				R848_Freq_Info.LPF_CAP = 8;
+				R848_Freq_Info.LPF_NOTCH = 4;
+			}
+			else if((LO_freq>=81000) && (LO_freq<89000))
+			{
+				R848_Freq_Info.LPF_CAP = 8;
+				R848_Freq_Info.LPF_NOTCH = 3;
+			}
+			else if((LO_freq>=89000) && (LO_freq<121000))
+			{
+				R848_Freq_Info.LPF_CAP = 6;
+				R848_Freq_Info.LPF_NOTCH = 1;
+			}
+			else if((LO_freq>=121000) && (LO_freq<145000))
+			{
+				R848_Freq_Info.LPF_CAP = 4;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else if((LO_freq>=145000) && (LO_freq<153000))
+			{
+				R848_Freq_Info.LPF_CAP = 3;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else if((LO_freq>=153000) && (LO_freq<177000))
+			{
+				R848_Freq_Info.LPF_CAP = 2;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else if((LO_freq>=177000) && (LO_freq<201000))
+			{
+				R848_Freq_Info.LPF_CAP = 1;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+			else //LO>=201M
+			{
+				R848_Freq_Info.LPF_CAP = 0;
+				R848_Freq_Info.LPF_NOTCH = 0;
+			}
+
+			break;
+
+	}//end switch(standard)
+
+	return R848_Freq_Info;
+
+}
+
+
+
+
+
+
+int I2C_Write(struct r848_priv *priv, I2C_TYPE *R848_I2C)
+{
+	
+	int ret = r848_wr(priv, R848_I2C->RegAddr, R848_I2C->Data);
+	if (ret)
+		return RT_Fail;
+	else
+		return RT_Success;
+}
+
+
+
+
+
+
+R848_ErrCode R848_Cal_Prepare( struct r848_priv *priv,u8 u1CalFlag)
+{
+	 R848_Cal_Info_Type  Cal_Info;
+	I2C_TYPE  R848_I2C;
+//	I2C_LEN_TYPE R848_I2C_Len;
+	u8 R848_IMR_Cal_Type = R848_IMR_CAL;
+	int ret;
+
+	 switch(u1CalFlag)
+	 {
+	    case R848_IMR_CAL:
+			    Cal_Info.FILTER_6DB = 0x08;              //+6dB		 R848:R38[3]
+				//Cal_Info.RFBUF_OUT = 0x60;            //from RF_Buf ON, RF_Buf pwr off		 // R848:R12[5]
+				//from RF_Buf ON, RF_Buf pwr off
+				Cal_Info.RFBUF_OUT = 0x20;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x04;				//RF_BUF_pwr OFF
+				Cal_Info.LNA_POWER = 0x80;              //LNA power OFF,RF_Buf pwr off  //  R848:R8[7]
+				//Cal_Info.LNA_POWER = 0x00;				//LNA need on
+				Cal_Info.TF_CAL = 0x00;					// TF cal OFF, -6dB	OFF   // R848:R14[6:5]
+				Cal_Info.MIXER_AMP_GAIN = 0x08;			//manual +8				  // R848:R15[4:0]
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10;		//manual min(0)			  // R848:R34[4:0]
+				Cal_Info.LNA_GAIN = 0x9F;                 //manual: max		//  R848:R13[7:0]
+				//Cal_Info.LNA_GAIN = 0x80;
+				R848_IMR_Cal_Type = R848_IMR_CAL;
+			break;
+		case R848_IMR_LNA_CAL:						    
+				Cal_Info.FILTER_6DB = 0x08;              //+6dB
+				//Cal_Info.RFBUF_OUT = 0x00;              //from RF_Buf ON, RF_Buf pwr on
+
+				Cal_Info.RFBUF_OUT = 0x00;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x00;				//RF_BUF_pwr OFF
+
+				Cal_Info.LNA_POWER = 0x80;             // LNA power OFF
+				//Cal_Info.LNA_POWER = 0x00;				//LNA need on
+				Cal_Info.TF_CAL = 0x60;				   // TF cal ON, -6dB ON
+				Cal_Info.MIXER_AMP_GAIN = 0x00;    //manual min(0)
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10; //manual min(0)
+				Cal_Info.LNA_GAIN = 0x9F;                 //manual: max
+				//Cal_Info.LNA_GAIN = 0x80;
+				R848_IMR_Cal_Type = R848_IMR_LNA_CAL;
+			break;
+        case R848_TF_CAL: //TBD
+			    Cal_Info.FILTER_6DB = 0x08;              //+6dB
+				//Cal_Info.RFBUF_OUT = 0x60;               //from RF_Buf ON, RF_Buf pwr off
+
+				Cal_Info.RFBUF_OUT = 0x20;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x04;				//RF_BUF_pwr OFF
+
+				Cal_Info.RFBUF_OUT = 0x20;
+				Cal_Info.LNA_POWER = 0x80;              //LNA power OFF
+				//Cal_Info.LNA_POWER = 0x00;				//LNA need on
+				Cal_Info.TF_CAL = 0x00;					//TF cal OFF, -6dB OFF	
+				Cal_Info.MIXER_AMP_GAIN = 0x00;    //manual min(0)
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10; //manual min(0)
+				Cal_Info.LNA_GAIN = 0x9F;                  //manual: max
+			break;
+        case R848_TF_LNA_CAL:
+			    Cal_Info.FILTER_6DB = 0x08;              //+6dB				
+				//Cal_Info.RFBUF_OUT = 0x00;              //from RF_Buf ON, RF_Buf pwr on	
+
+				Cal_Info.RFBUF_OUT = 0x00;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x00;				//RF_BUF_pwr OFF
+
+				Cal_Info.LNA_POWER = 0x80;              //LNA power OFF
+				//Cal_Info.LNA_POWER = 0x00;				//LNA need on
+				Cal_Info.TF_CAL = 0x60;					// TF cal ON, -6dB ON	
+				Cal_Info.MIXER_AMP_GAIN = 0x00;    //manual min(0)
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10; //manual min(0)
+				Cal_Info.LNA_GAIN = 0x80;                  //manual: min
+			break;
+		case R848_LPF_CAL: 
+			    Cal_Info.FILTER_6DB = 0x08;              //+6dB						//  R848:R38[3]
+				//Cal_Info.RFBUF_OUT = 0x60;               //from RF_Buf ON, RF_Buf pwr off
+				//Cal_Info.RFBUF_OUT = 0x20;				//RF_Buf pwr off			//  R848:R12[5]
+				Cal_Info.RFBUF_OUT = 0x20;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x04;				//RF_BUF_pwr OFF
+
+				Cal_Info.LNA_POWER = 0x80;              //LNA power OFF, TF cal OFF, -6dB OFF	
+				//Cal_Info.LNA_POWER = 0x00;              //LNA need on			   //  R848:R8[7]
+				Cal_Info.TF_CAL = 0x00;					// TF cal OFF, -6dB OFF		// R848:R14[6:5]
+				Cal_Info.MIXER_AMP_GAIN = 0x08;    //manual +8						// R848:R15[4:0]
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10; //manual min(0)					// R848:R34[4:0]	
+				Cal_Info.LNA_GAIN = 0x9F;                 //manual: max				// R848:R13[7:0]
+				R848_IMR_Cal_Type = R848_LPF_CAL;
+			break;
+		case R848_LPF_LNA_CAL:
+			    Cal_Info.FILTER_6DB = 0x08;              //+6dB
+				//Cal_Info.RFBUF_OUT = 0x00;               //from RF_Buf ON, RF_Buf pwr on
+				Cal_Info.RFBUF_OUT = 0x00;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x00;				//RF_BUF_pwr OFF
+				Cal_Info.LNA_POWER = 0x80;              //LNA power OFF
+				//Cal_Info.LNA_POWER = 0x00;              //LNA need on
+				Cal_Info.TF_CAL = 0x20;					// TF cal ON, -6dB OFF	
+				Cal_Info.MIXER_AMP_GAIN = 0x00;    //manual min(0)
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10; //manual min(0)
+				Cal_Info.LNA_GAIN = 0x80;                  //manual: min
+			break;
+		default:
+			    Cal_Info.FILTER_6DB = 0x08;              //+6dB
+				//Cal_Info.RFBUF_OUT = 0x60;               //from RF_Buf ON, RF_Buf pwr off
+				Cal_Info.RFBUF_OUT = 0x20;				//from RF_Buf ON
+				Cal_Info.RFBUF_POWER=0x04;				//RF_BUF_pwr OFF
+				Cal_Info.LNA_POWER = 0x80;              //LNA power OFF
+				//Cal_Info.LNA_POWER = 0x00;              //LNA need on
+				Cal_Info.TF_CAL = 0x00;					//TF cal OFF, -6dB OFF
+				Cal_Info.MIXER_AMP_GAIN = 0x08;    //manual +8
+				Cal_Info.MIXER_BUFFER_GAIN = 0x10; //manual min(0)
+				Cal_Info.LNA_GAIN = 0x9F;                 //manual: max
+	 }
+
+	  //Ring From RF_Buf Output & RF_Buf Power
+	  //R848_I2C.RegAddr = 0x0C;
+      priv->cfg->R848_Array[4] = (priv->cfg->R848_Array[4] & 0xDF) | Cal_Info.RFBUF_OUT;   //  R848:R12[5]  12-8=4  12(0x0C) is addr ; [4] is data
+      //R848_I2C.Data = priv->cfg->R848_Array[4];
+
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+      //    return RT_Fail; 
+	ret = r848_wr(priv, 0x0c, priv->cfg->R848_Array[4]);
+	if (ret)
+		return ret;
+
+
+	  //RF_Buf Power
+	  //R848_I2C.RegAddr = 0x09;
+      priv->cfg->R848_Array[1] = (priv->cfg->R848_Array[1] & 0xFB) | Cal_Info.RFBUF_POWER;
+      //R848_I2C.Data = priv->cfg->R848_Array[1];
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+      //    return RT_Fail; 
+	ret = r848_wr(priv, 0x09, priv->cfg->R848_Array[1]);
+	if (ret)
+		return ret;
+  
+	  /*//TF cal (LNA power ON/OFF , TF cal ON/OFF, TF_-6dB ON/OFF)
+	  R848_I2C.RegAddr = 0x06;
+      priv->cfg->R848_Array[6] = (priv->cfg->R848_Array[6] & 0x1F) | Cal_Info.LNA_POWER;
+      R848_I2C.Data = priv->cfg->R848_Array[6];
+      if(I2C_Write(&R848_I2C) != RT_Success)
+          return RT_Fail; */
+
+
+	  //(LNA power ON/OFF )
+	  //R848_I2C.RegAddr = 0x08;
+      priv->cfg->R848_Array[0] = (priv->cfg->R848_Array[0] & 0x7F) | Cal_Info.LNA_POWER;	 //  R848:R8[7]  8-8=0  8(0x08) is addr ; [0] is data
+	  //priv->cfg->R848_Array[0] = (priv->cfg->R848_Array[0] & 0x80) 	 // R848:R8[7]  8-8=0  14(0x08) is addr ; [0] is data
+      //R848_I2C.Data = priv->cfg->R848_Array[0];
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+       //   return RT_Fail;
+	ret = r848_wr(priv, 0x08, priv->cfg->R848_Array[0]);
+	if (ret)
+		return ret;
+
+
+	  //TF cal (TF cal ON/OFF, TF_-6dB ON/OFF)
+	//  R848_I2C.RegAddr = 0x0E;
+      priv->cfg->R848_Array[6] = (priv->cfg->R848_Array[6] & 0x9F) | Cal_Info.TF_CAL;	 // R848:R14[6:5]  14-8=6  14(0x0E) is addr ; [6] is data
+      //R848_I2C.Data = priv->cfg->R848_Array[6];
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+      //    return RT_Fail;
+	ret = r848_wr(priv, 0x0e, priv->cfg->R848_Array[6]);
+	if (ret)
+		return ret;
+
+
+	  //LNA gain
+	//  R848_I2C.RegAddr = 0x0D;
+	  priv->cfg->R848_Array[5] = (priv->cfg->R848_Array[5] & 0x60) | Cal_Info.LNA_GAIN; // R848:R13[7:0]  13-8=5  13(0x0D) is addr ; [5] is data
+     // R848_I2C.Data = priv->cfg->R848_Array[5];
+     // if(I2C_Write(priv,&R848_I2C) != RT_Success)
+     //     return RT_Fail;
+	ret = r848_wr(priv, 0x0d, priv->cfg->R848_Array[5]);
+	if (ret)
+		return ret;
+
+
+	  //Mixer Amp Gain
+	  //R848_I2C.RegAddr = 0x0F;
+	  priv->cfg->R848_Array[7] = (priv->cfg->R848_Array[7] & 0xE0) | Cal_Info.MIXER_AMP_GAIN; // R848:R15[4:0]  15-8=7  15(0x0F) is addr ; [7] is data
+      //R848_I2C.Data = priv->cfg->R848_Array[7];
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+      //    return RT_Fail;
+	ret = r848_wr(priv, 0x0f, priv->cfg->R848_Array[7]);
+	if (ret)
+		return ret;
+
+
+	  //Mixer Buffer Gain
+	  //R848_I2C.RegAddr = 0x22;								// R848:R34[4:0]  34-8=26  34(0x22) is addr ; [26] is data
+	  priv->cfg->R848_Array[26] = (priv->cfg->R848_Array[26] & 0xE0) | Cal_Info.MIXER_BUFFER_GAIN;  
+      //R848_I2C.Data = priv->cfg->R848_Array[26];
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+      //    return RT_Fail;	 
+	ret = r848_wr(priv, 0x22, priv->cfg->R848_Array[26]);
+	if (ret)
+		return ret;
+
+	  // Set filter +0/6dB; NA det=OFF 
+      //R848_I2C.RegAddr  = 0x26;								// R848:R38[3]  38-8=30  38(0x26) is addr ; [30] is data
+	  priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0xF7) | Cal_Info.FILTER_6DB | 0x80;
+     // R848_I2C.Data = priv->cfg->R848_Array[30];
+     // if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	//     return RT_Fail;
+	ret = r848_wr(priv, 0x26, priv->cfg->R848_Array[30]);
+	if (ret)
+		return ret;
+
+	  //Set NA det 710 = OFF
+	//  R848_I2C.RegAddr  = 0x28;								// R848:R40[3]  40-8=32  40(0x28) is addr ; [32] is data
+	  priv->cfg->R848_Array[32] = (priv->cfg->R848_Array[32] | 0x08);
+      //R848_I2C.Data = priv->cfg->R848_Array[32];
+      //if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	//     return RT_Fail;
+	ret = r848_wr(priv, 0x28, priv->cfg->R848_Array[32]);
+	if (ret)
+		return ret;
+
+
+	 //---- General calibration setting ----//	 
+	 //IMR IQ cap=0
+//	 R848_I2C.RegAddr = 0x0B;		//R848:R11[1:0]  11-8=3  11(0x0B) is addr ; [3] is data
+     priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xFC);
+//     R848_I2C.Data = priv->cfg->R848_Array[3];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//          return RT_Fail;
+	ret = r848_wr(priv, 0x0b, priv->cfg->R848_Array[3]);
+	if (ret)
+		return ret;
+
+	 // Set RF_Flag ON(%)
+//	 R848_I2C.RegAddr = 0x16;		//R848:R22[0]  22-8=14  22(0x16) is addr ; [14] is data
+     priv->cfg->R848_Array[14] = priv->cfg->R848_Array[14] | 0x01;  //force far-end mode
+//     R848_I2C.Data = priv->cfg->R848_Array[14];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+ //         return RT_Fail;
+	ret = r848_wr(priv, 0x16, priv->cfg->R848_Array[14]);
+	if (ret)
+		return ret;
+
+	 //RingPLL power ON
+//     R848_I2C.RegAddr = 0x12;	  //R848:R18[4]  18-8=10  18(0x12) is addr ; [10] is data
+     priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xEF);
+//     R848_I2C.Data = priv->cfg->R848_Array[10];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x12, priv->cfg->R848_Array[10]);
+	if (ret)
+		return ret;
+
+	 //LPF filter code = 15
+//     R848_I2C.RegAddr = 0x12;	//R848:R18[3:0]  18-8=10  18(0x12) is addr ; [10] is data
+     priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xF0) | 0x0F;
+//     R848_I2C.Data = priv->cfg->R848_Array[10];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x12, priv->cfg->R848_Array[10]);
+	if (ret)
+		return ret;
+	 
+     //HPF corner=narrowest; LPF coarse=6M; 1.7M disable
+//     R848_I2C.RegAddr = 0x13;	//R848:R19[7:0]  19-8=11  19(0x13) is addr ; [11] is data
+     priv->cfg->R848_Array[11] = (priv->cfg->R848_Array[11] & 0x00) | 0x60;
+//     R848_I2C.Data = priv->cfg->R848_Array[11];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x13, priv->cfg->R848_Array[11]);
+	if (ret)
+		return ret;
+
+     //ADC/VGA PWR on; Vga code mode(b4=1), Gain = 26.5dB; Large Code mode Gain(b5=1)
+	 //ADC PWR on (b7=0)
+//	 R848_I2C.RegAddr = 0x0F;	//R848:R15[7]  15-8=7  15(0x0F) is addr ; [7] is data
+     priv->cfg->R848_Array[7] = (priv->cfg->R848_Array[7] & 0x7F);
+//     R848_I2C.Data = priv->cfg->R848_Array[7];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x0f, priv->cfg->R848_Array[7]);
+	if (ret)
+		return ret;
+
+	 //VGA PWR on (b0=0)
+	 //R848_I2C.RegAddr = 0x09;	// R848:R9[0]  9-8=1  9(0x09) is addr ; [1] is data
+     //priv->cfg->R848_Array[1] = (priv->cfg->R848_Array[1] & 0xFE);  
+     //R848_I2C.Data = priv->cfg->R848_Array[1];
+     //if(I2C_Write(&R848_I2C) != RT_Success)
+     //      return RT_Fail;
+
+	 //VGA PWR on (b0=0)  MT2
+//	 R848_I2C.RegAddr = 0x12;	//R848:R18[7]  9-8=1  9(0x09) is addr ; [1] is data
+     priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0x7F);  
+//     R848_I2C.Data = priv->cfg->R848_Array[10];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x12, priv->cfg->R848_Array[10]);
+	if (ret)
+		return ret;
+
+	 //Large Code mode Gain(b5=1)
+//	 R848_I2C.RegAddr = 0x0B;	//R848:R11[3]  11-8=3  11(0x0B) is addr ; [3] is data
+     priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xF7) | 0x08;  
+//     R848_I2C.Data = priv->cfg->R848_Array[3];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x0b, priv->cfg->R848_Array[3]);
+	if (ret)
+		return ret;
+
+	 //Vga code mode(b4=1)
+//	 R848_I2C.RegAddr = 0x09;	//R848:R9[1]  9-8=1  9(0x09) is addr ; [1] is data
+     priv->cfg->R848_Array[1] = (priv->cfg->R848_Array[1] & 0xFD) | 0x02;  
+//     R848_I2C.Data = priv->cfg->R848_Array[1];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x09, priv->cfg->R848_Array[1]);
+	if (ret)
+		return ret;
+
+	 //Gain = 26.5dB
+//     R848_I2C.RegAddr = 0x14;	//R848:R20[3:0]  20-8=12  20(0x14) is addr ; [12] is data
+     priv->cfg->R848_Array[12] = (priv->cfg->R848_Array[12] & 0xF0) | 0x0B;  
+//     R848_I2C.Data = priv->cfg->R848_Array[12];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x14, priv->cfg->R848_Array[12]);
+	if (ret)
+		return ret;
+
+
+
+	 //LNA, RF, Nrb dector pw on; det2 cap=IF_det 
+//     R848_I2C.RegAddr = 0x25;	//R848:R37[3:0]  37-8=29  37(0x25) is addr ; [29] is data
+     priv->cfg->R848_Array[29] = (priv->cfg->R848_Array[29] & 0xF0) | 0x02;
+//     R848_I2C.Data = priv->cfg->R848_Array[29];
+//     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//           return RT_Fail;
+	ret = r848_wr(priv, 0x25, priv->cfg->R848_Array[29]);
+	if (ret)
+		return ret;
+
+      return RT_Success;
+}
+
+R848_ErrCode R848_Xtal_Check( struct r848_priv *priv)
+{
+	u8 i = 0;
+	I2C_TYPE  R848_I2C;
+	I2C_LEN_TYPE R848_I2C_Len;
+
+	u8 buf[3];
+	int ret;
+
+	// TF force sharp mode (for stable read)
+//	R848_I2C.RegAddr = 0x16;
+	priv->cfg->R848_Array[14] = priv->cfg->R848_Array[14] | 0x01;    
+//	R848_I2C.Data = priv->cfg->R848_Array[14];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x16, priv->cfg->R848_Array[14]);
+	if (ret)
+		return ret;
+
+	// NA det off (for stable read)
+//	R848_I2C.RegAddr = 0x26;
+	priv->cfg->R848_Array[30] = priv->cfg->R848_Array[30] | 0x80;  
+//	R848_I2C.Data = priv->cfg->R848_Array[30];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x26, priv->cfg->R848_Array[30]);
+	if (ret)
+		return ret;
+
+	//Set NA det 710 = OFF
+//	R848_I2C.RegAddr  = 0x28;								
+	priv->cfg->R848_Array[32] = (priv->cfg->R848_Array[32] | 0x08);
+//    R848_I2C.Data = priv->cfg->R848_Array[32];
+//    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x28, priv->cfg->R848_Array[32]);
+	if (ret)
+		return ret;
+	
+	// Xtal_pow=lowest(11)  R848:R23[6:5]
+//	R848_I2C.RegAddr = 0x17;
+	priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x9F) | 0x60;
+//	R848_I2C.Data = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+
+	//Xtal_Gm=SMALL(0) R848:R27[0]
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | 0x00;
+//	R848_I2C.Data = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+
+
+	//set pll autotune = 128kHz  R848:R23[4:3]
+//	R848_I2C.RegAddr = 0x17;
+	priv->cfg->R848_Array[15] = priv->cfg->R848_Array[15] & 0xE7;
+//	R848_I2C.Data = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+
+	//set manual initial reg = 1 000000; b5=0 => cap 30p;		 R848:R27[7:0]
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0x80) | 0x40;
+//	R848_I2C.Data = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+
+	//set auto
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xBF);
+//	R848_I2C.Data = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+	
+	msleep(10);
+
+
+	// Xtal_pow=lowest(11) R848:R23[6:5]
+//	R848_I2C.RegAddr = 0x17;
+	priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x9F) | 0x60;
+//	R848_I2C.Data = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+
+	//Xtal_Gm=SMALL(0) R848:R27[0]
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | 0x00;
+//	R848_I2C.Data = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+
+
+
+
+	for(i=0; i<XTAL_CHECK_SIZE; i++)
+	{
+	    //set power
+		if(i<=XTAL_SMALL_HIGHEST)
+		{
+			priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x9F) | ((u8)(XTAL_SMALL_HIGHEST-i)<<5) ;   
+			priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | 0x00 ;		//| 0x00;  //SMALL Gm(0)
+		}
+		else if(i==XTAL_LARGE_HIGHEST)
+		{
+			//priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x87) | 0x00 | 0x18;  //3v Gm, highest
+			priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x9F) | 0X00 ;   
+			priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | 0x01 ;		//| 0x00;  //LARGE Gm(1)
+		}
+		else
+		{
+            //priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x87) | 0x00 | 0x18;  //3v Gm, highest
+			priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0x9F) | 0X00 ;   
+			priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | 0x01 ;		//| 0x00;  //LARGE Gm(1)
+		}
+
+
+//		R848_I2C.RegAddr = 0x17;
+//		R848_I2C.Data = priv->cfg->R848_Array[15];
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			return RT_Fail;
+		ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+		if (ret)
+			return ret;
+
+//		R848_I2C.RegAddr = 0x1B;
+//		R848_I2C.Data = priv->cfg->R848_Array[19];
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			return RT_Fail;
+		ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+		if (ret)
+			return ret;
+
+
+		msleep(50);
+
+		//R848_I2C_Len.RegAddr = 0x00;
+		//R848_I2C_Len.Len = 3;
+		//if(I2C_Read_Len(priv,&R848_I2C_Len) != RT_Success)
+		//{
+		//	if(I2C_Read_Len(priv,&R848_I2C_Len) != RT_Success)
+		//		return RT_Fail;
+		//}
+		ret = r848_rdm(priv, 0x00, buf, 3);
+			
+
+		//depend on init Nint & Div value (N=59.6667, Div=16)
+		//lock to VCO band 8 if VCO=2768M for 16M Xtal
+		//lock to VCO band 46 if VCO=2768M for 24M Xtal
+#if(R848_Xtal==16000)
+		if(((buf[2] & 0x40) == 0x40) && ((buf[2] & 0x3F) <= 11) && ((buf[2] & 0x3F) >= 5))  
+#else
+		if(((buf[2] & 0x40) == 0x40) && ((buf[2] & 0x3F) <= 48) && ((buf[2] & 0x3F) >= 42)) 
+#endif
+		{
+		    priv->cfg->R848_Xtal_Pwr_tmp = i;
+			break;
+		}
+
+	    if(i==(XTAL_CHECK_SIZE-1))
+		{
+	        priv->cfg->R848_Xtal_Pwr_tmp = i;
+		}
+	}
+
+
+    return RT_Success;
+}	
+
+
+R848_ErrCode R848_PLL( struct r848_priv *priv,u32 LO_Freq, R848_Standard_Type R848_Standard)
+{
+	int ret;
+	u8 buf[3];
+
+	u8  MixDiv = 2;
+	u8  DivBuf = 0;
+	u8  Ni = 0;
+	u8  Si = 0;
+	u8  DivNum = 0;
+	u16  Nint = 0;
+	u32 VCO_Min = 2410000; 
+	u32 VCO_Max = VCO_Min*2;
+	u32 VCO_Freq = 0;
+	u32 PLL_Ref	= R848_Xtal;		
+	u32 VCO_Fra	= 0;		
+	u16 Nsdm = 2;
+	u16 SDM = 0;
+	u16 SDM16to9 = 0;
+	u16 SDM8to1 = 0;
+	u8   CP_CUR = 0x00;
+	u8   CP_OFFSET = 0x00;
+	u8   SDM_RES = 0x00;
+	u8   XTAL_POW1 = 0x00;
+	u8   XTAL_POW0 = 0x00;
+	u8   XTAL_GM = 0x00;
+	u16  u2XalDivJudge;
+	u8   u1XtalDivRemain;
+	u8   VCO_current_trial = 0;
+
+	u8   u1RfFlag = 0;
+	u8   u1PulseFlag = 0;
+	u8   u1SPulseFlag=0;
+
+
+	u8	R848_XtalDiv = XTAL_DIV2;
+
+	
+	I2C_TYPE  R848_I2C;
+	I2C_LEN_TYPE R848_I2C_Len;
+
+	//TF, NA fix
+	u1RfFlag = (priv->cfg->R848_Array[14] & 0x01);         //R22[0]
+	u1PulseFlag = (priv->cfg->R848_Array[30] & 0x80);   //R38[7]
+	u1SPulseFlag= (priv->cfg->R848_Array[32] & 0x08);   //R40[3]
+
+
+//	R848_I2C.RegAddr = 0x16;
+	priv->cfg->R848_Array[14] = priv->cfg->R848_Array[14] | 0x01;		// TF force sharp mode
+//	R848_I2C.Data = priv->cfg->R848_Array[14];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x16, priv->cfg->R848_Array[14]);
+	if (ret)
+		return ret;
+
+
+//	R848_I2C.RegAddr = 0x26;
+	priv->cfg->R848_Array[30] = priv->cfg->R848_Array[30] | 0x80;		// NA det off
+//	R848_I2C.Data = priv->cfg->R848_Array[30];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x26, priv->cfg->R848_Array[30]);
+	if (ret)
+		return ret;
+
+	//Set NA det 710 = OFF
+//	R848_I2C.RegAddr  = 0x28;								
+	priv->cfg->R848_Array[32] = (priv->cfg->R848_Array[32] | 0x08);
+//    R848_I2C.Data = priv->cfg->R848_Array[32];
+//    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	   return RT_Fail;
+	ret = r848_wr(priv, 0x28, priv->cfg->R848_Array[32]);
+	if (ret)
+		return ret;
+
+	//DTV
+	CP_CUR = 0x00;     //0.7m, R25[6:4]=000
+	CP_OFFSET = 0x00;  //0u,     [2]=0
+	
+	//CP current  R25[6:4]=000
+//	R848_I2C.RegAddr = 0x19; 
+	priv->cfg->R848_Array[17]    = (priv->cfg->R848_Array[17] & 0x8F)  | CP_CUR ;
+//	R848_I2C.Data    = priv->cfg->R848_Array[17];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x19, priv->cfg->R848_Array[17]);
+	if (ret)
+		return ret;
+
+
+	//Div Cuurent   R20[7:6]=2'b01(150uA)	
+//	R848_I2C.RegAddr = 0x14;    
+	priv->cfg->R848_Array[12]    = (priv->cfg->R848_Array[12] & 0x3F)  | 0x40;  
+//	R848_I2C.Data    = priv->cfg->R848_Array[12];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x14, priv->cfg->R848_Array[12]);
+	if (ret)
+		return ret;
+
+
+	//CPI*2 R28[7]=1
+	if((R848_Standard!=R848_DVB_S) && (LO_Freq >= 865000))
+	{
+//		R848_I2C.RegAddr = 0x1C;
+		priv->cfg->R848_Array[20] = (priv->cfg->R848_Array[20] & 0x7F) | 0x80;
+//		R848_I2C.Data = priv->cfg->R848_Array[20];
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+		ret = r848_wr(priv, 0x1c, priv->cfg->R848_Array[20]);
+		if (ret)
+			return ret;
+		}
+	else
+	{
+//		R848_I2C.RegAddr = 0x1C;
+		priv->cfg->R848_Array[20] = (priv->cfg->R848_Array[20] & 0x7F);
+//		R848_I2C.Data = priv->cfg->R848_Array[20];
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+		ret = r848_wr(priv, 0x1c, priv->cfg->R848_Array[20]);
+		if (ret)
+			return ret;
+		}
+
+	//  R848:R26[7:5]  VCO_current= 2
+//	R848_I2C.RegAddr = 0x1A;  
+	priv->cfg->R848_Array[18]    = (priv->cfg->R848_Array[18] & 0x1F) | 0x40; 
+//	R848_I2C.Data    = priv->cfg->R848_Array[18];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x1a, priv->cfg->R848_Array[18]);
+	if (ret)
+		return ret;
+
+
+	//CP Offset R21[7] 
+//	R848_I2C.RegAddr = 0x15;  
+	priv->cfg->R848_Array[13]    = (priv->cfg->R848_Array[13] & 0x7F) | CP_OFFSET; 
+//	R848_I2C.Data    = priv->cfg->R848_Array[13];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x15, priv->cfg->R848_Array[13]);
+	if (ret)
+		return ret;
+
+	//if(R848_Initial_done_flag==TRUE)
+	{
+		//set XTAL Power
+		if((priv->cfg->R848_Xtal_Pwr<XTAL_SMALL_HIGH) && (LO_Freq > (64000+8500)))
+		{			
+				XTAL_POW1 = 0x00;        //high,       R16[4]=0  //R848:R23[7] 
+				XTAL_POW0 = 0x20;        //high,       R15[6:5]=01  //R848:R23[6:5] 
+				XTAL_GM = 0x00;            //SMALL(0),   R15[4:3]=00		
+		}
+		else
+		{
+			if(priv->cfg->R848_Xtal_Pwr <= XTAL_SMALL_HIGHEST)
+			{
+				XTAL_POW1 = 0x00;        //high,       R16[4]=0	// R848:R23[7]    
+				XTAL_POW0 = ((u8)(XTAL_SMALL_HIGHEST-priv->cfg->R848_Xtal_Pwr)<<5);	//R848:R23[6:5]      
+				XTAL_GM = 0x00;            //SMALL(0),   R27[0]=0
+			}
+			else if(priv->cfg->R848_Xtal_Pwr == XTAL_LARGE_HIGHEST)
+			{
+				XTAL_POW1 = 0x00;        //high,      	// R848:R23[7]  
+				XTAL_POW0 = 0x00;        //highest,  	// R848:R23[6:5] 
+				XTAL_GM = 0x01;            //LARGE(1),         R27[0]=1
+			}
+			else
+			{
+				XTAL_POW1 = 0x00;        //high,     // R848:R23[7]    
+				XTAL_POW0 = 0x00;        //highest,  // R848:R23[6:5]
+				XTAL_GM = 0x01;            //LARGE(1),         R27[0]=1
+			}
+		}
+	}
+//	else
+//	{
+//		XTAL_POW1 = 0x00;        //high,      	// R848:R23[7]  
+//		XTAL_POW0 = 0x00;        //highest,  	// R848:R23[6:5] 
+//		XTAL_GM = 0x01;          //LARGE(1),         R27[0]=1
+//	}
+
+	//Xtal_Gm=SMALL(0) R27[0]
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | XTAL_GM;
+//	R848_I2C.Data = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x17;		// R23[6:5]  
+	priv->cfg->R848_Array[15]    = (priv->cfg->R848_Array[15] & 0x9F) | XTAL_POW0; 
+//	R848_I2C.Data    = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x17;		// R23[7]   
+	priv->cfg->R848_Array[15]    = (priv->cfg->R848_Array[15] & 0x7F) | XTAL_POW1; 
+//	R848_I2C.Data    = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+
+	//IQ gen ON 
+//	R848_I2C.RegAddr = 0x27;		// R39[1]
+	priv->cfg->R848_Array[31]    = (priv->cfg->R848_Array[31] & 0xFD) | 0x00; //[0]=0'b0
+//	R848_I2C.Data    = priv->cfg->R848_Array[31];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x27, priv->cfg->R848_Array[31]);
+	if (ret)
+		return ret;
+
+	// current:Dmin, Bmin
+//	R848_I2C.RegAddr = 0x23;		// R848:R35[5:4]=2'b00
+	priv->cfg->R848_Array[27]    = (priv->cfg->R848_Array[27] & 0xCF) | 0x00;
+//	R848_I2C.Data    = priv->cfg->R848_Array[27];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x23, priv->cfg->R848_Array[27]);
+	if (ret)
+		return ret;
+
+	//set pll autotune = 128kHz (fast)  R23[4:3]=2'b00   
+//	R848_I2C.RegAddr = 0x17;		
+	priv->cfg->R848_Array[15]    = priv->cfg->R848_Array[15] & 0xE7;
+//	R848_I2C.Data    = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+
+	//Divider
+	while(MixDiv <= 64)
+	{
+		if(((LO_Freq * MixDiv) >= VCO_Min) && ((LO_Freq * MixDiv) < VCO_Max))
+		{
+			DivBuf = MixDiv;
+			while(DivBuf > 2)
+			{
+				DivBuf = DivBuf >> 1;
+				DivNum ++;
+			}			
+			break;
+		}
+		MixDiv = MixDiv << 1;
+	}
+
+	SDM_RES = 0x00;    //short, R27[4:3]=00
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19]    = (priv->cfg->R848_Array[19] & 0xE7) | SDM_RES; 
+//	R848_I2C.Data    = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+
+	//Xtal Div
+	if(R848_Standard == R848_STD_SIZE) //for cal
+	{
+		    R848_XtalDiv = XTAL_DIV1;
+	        priv->cfg->R848_Array[16] = priv->cfg->R848_Array[16] & 0xFB; //b2=0  // R848:R24[2]   
+	        PLL_Ref = R848_Xtal;
+	}
+	else	//DTV_Standard
+	{
+		    u2XalDivJudge = (u16) (LO_Freq/1000/8);
+			u1XtalDivRemain = (u8) (u2XalDivJudge % 2);
+		   if(u1XtalDivRemain==1) //odd
+		   {
+				R848_XtalDiv = XTAL_DIV1;
+				priv->cfg->R848_Array[16] = priv->cfg->R848_Array[16] & 0xFB; //R24[2]=0  
+				PLL_Ref = R848_Xtal;
+			}
+			else  // div2, note that agc clk also div2
+			{
+
+			   R848_XtalDiv = XTAL_DIV2;
+				priv->cfg->R848_Array[16] |= 0x04;   	//R24[2]=1
+				PLL_Ref = R848_Xtal / 2;
+				
+			}	
+	}
+
+//	R848_I2C.RegAddr = 0x18;	//R848:R24[2] 
+//	R848_I2C.Data = priv->cfg->R848_Array[16];
+//    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	   return RT_Fail;
+	ret = r848_wr(priv, 0x18, priv->cfg->R848_Array[16]);
+	if (ret)
+		return ret;
+
+
+
+	//Divider num
+//	R848_I2C.RegAddr = 0x18; //R24[7:5] 
+	priv->cfg->R848_Array[16] &= 0x1F;
+	priv->cfg->R848_Array[16] |= (DivNum << 5);
+//	R848_I2C.Data = priv->cfg->R848_Array[16];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x18, priv->cfg->R848_Array[16]);
+	if (ret)
+		return ret;
+
+	VCO_Freq = LO_Freq * MixDiv;
+	Nint     = (u16) (VCO_Freq / 2 / PLL_Ref);
+	VCO_Fra  = (u16) (VCO_Freq - 2 * PLL_Ref * Nint);
+
+	//Boundary spur prevention
+	if (VCO_Fra < PLL_Ref/64)           //2*PLL_Ref/128
+		VCO_Fra = 0;
+	else if (VCO_Fra > PLL_Ref*127/64)  //2*PLL_Ref*127/128
+	{
+		VCO_Fra = 0;
+		Nint ++;
+	}
+	else if((VCO_Fra > PLL_Ref*127/128) && (VCO_Fra < PLL_Ref)) //> 2*PLL_Ref*127/256,  < 2*PLL_Ref*128/256
+		VCO_Fra = PLL_Ref*127/128;      // VCO_Fra = 2*PLL_Ref*127/256
+	else if((VCO_Fra > PLL_Ref) && (VCO_Fra < PLL_Ref*129/128)) //> 2*PLL_Ref*128/256,  < 2*PLL_Ref*129/256
+		VCO_Fra = PLL_Ref*129/128;      // VCO_Fra = 2*PLL_Ref*129/256
+	else
+		VCO_Fra = VCO_Fra;
+
+	//Ni:R848:R28[6:0]   Si:R848:R20[5:4]
+	Ni = (Nint - 13) / 4;
+	Si = Nint - 4 *Ni - 13;
+	//Si
+//	R848_I2C.RegAddr = 0x14;
+	priv->cfg->R848_Array[12] = (priv->cfg->R848_Array[12] & 0xCF) | ((Si << 4));
+//	R848_I2C.Data = priv->cfg->R848_Array[12];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	  return RT_Fail;
+	ret = r848_wr(priv, 0x14, priv->cfg->R848_Array[12]);
+	if (ret)
+		return ret;
+	//Ni
+//	R848_I2C.RegAddr = 0x1C;
+	priv->cfg->R848_Array[20] = (priv->cfg->R848_Array[20] & 0x80) | (Ni);
+//	R848_I2C.Data = priv->cfg->R848_Array[20];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	  return RT_Fail;
+	ret = r848_wr(priv, 0x1c, priv->cfg->R848_Array[20]);
+	if (ret)
+		return ret;
+
+         	
+	//pw_sdm		// R848:R27[7]  
+//	R848_I2C.RegAddr = 0x1B;
+	priv->cfg->R848_Array[19] &= 0x7F;
+	if(VCO_Fra == 0)
+		priv->cfg->R848_Array[19] |= 0x80;
+//	R848_I2C.Data = priv->cfg->R848_Array[19];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+	if (ret)
+		return ret;
+
+	//SDM calculator
+	while(VCO_Fra > 1)
+	{			
+		if (VCO_Fra > (2*PLL_Ref / Nsdm))
+		{		
+			SDM = SDM + 32768 / (Nsdm/2);
+			VCO_Fra = VCO_Fra - 2*PLL_Ref / Nsdm;
+			if (Nsdm >= 0x8000)
+				break;
+		}
+		Nsdm = Nsdm << 1;
+	}
+
+	SDM16to9 = SDM >> 8;
+	SDM8to1 =  SDM - (SDM16to9 << 8);
+
+	// R848:R30[7:0]  
+//	R848_I2C.RegAddr = 0x1E;
+	priv->cfg->R848_Array[22]    = (u8) SDM16to9;
+//	R848_I2C.Data    = priv->cfg->R848_Array[22];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x1e, priv->cfg->R848_Array[22]);
+	if (ret)
+		return ret;
+	//R848:R29[7:0] 
+//	R848_I2C.RegAddr = 0x1D;
+	priv->cfg->R848_Array[21]    = (u8) SDM8to1;
+//	R848_I2C.Data    = priv->cfg->R848_Array[21];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x1d, priv->cfg->R848_Array[21]);
+	if (ret)
+		return ret;
+
+
+	//if(R848_Standard <= R848_SECAM_L1_INV)
+	if(R848_XtalDiv == XTAL_DIV2)
+	    msleep(20);
+	else
+	    msleep(10);
+
+	for(VCO_current_trial=0; VCO_current_trial<3; VCO_current_trial++)
+	{
+		//check PLL lock status 
+//		R848_I2C_Len.RegAddr = 0x00;
+//		R848_I2C_Len.Len = 3;
+//		if(I2C_Read_Len(priv,&R848_I2C_Len) != RT_Success)
+//		{	
+//			I2C_Read_Len(priv,&R848_I2C_Len);
+//		}
+		ret = r848_rdm(priv, 0x00, buf, 3);
+		if (ret)
+			return ret;
+
+		// R848:R26[7:5] 
+		if( (buf[2] & 0x40) == 0x00 ) 
+		{
+			//Set VCO current = 011 (3)
+//			R848_I2C.RegAddr = 0x1A;
+			//priv->cfg->R848_Array[18]    = (priv->cfg->R848_Array[18] & 0x1F) | 0x60;  //increase VCO current
+			priv->cfg->R848_Array[18]    = (priv->cfg->R848_Array[18] & 0x1F) | ((2-VCO_current_trial) << 5);  //increase VCO current
+//			R848_I2C.Data    = priv->cfg->R848_Array[18];
+//			if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//				return RT_Fail;
+			ret = r848_wr(priv, 0x1a, priv->cfg->R848_Array[18]);
+			if (ret)
+				return ret;
+		}
+	}
+
+	if(VCO_current_trial==2)
+	{
+		//check PLL lock status 
+//		R848_I2C_Len.RegAddr = 0x00;
+//		R848_I2C_Len.Len = 3;
+//		if(I2C_Read_Len(priv,&R848_I2C_Len) != RT_Success)
+//			return RT_Fail;
+		ret = r848_rdm(priv, 0x00, buf, 3);
+		if (ret)
+			return ret;
+
+
+		if( (buf[2] & 0x40) == 0x00) 
+		{
+			if(priv->cfg->R848_Xtal_Pwr <= XTAL_SMALL_HIGHEST)
+				XTAL_GM = 0x01;            //LARGE(1),         R15[4:3]=11
+
+//			R848_I2C.RegAddr = 0x1B;
+			priv->cfg->R848_Array[19] = (priv->cfg->R848_Array[19] & 0xFE) | XTAL_GM;
+//			R848_I2C.Data = priv->cfg->R848_Array[19];
+//			if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//				return RT_Fail;
+			ret = r848_wr(priv, 0x1b, priv->cfg->R848_Array[19]);
+			if (ret)
+				return ret;
+		}
+	}
+
+	//set pll autotune = 8kHz (slow)
+//	R848_I2C.RegAddr = 0x17;
+	priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0xE7) | 0x10;
+//	R848_I2C.Data = priv->cfg->R848_Array[15];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x17, priv->cfg->R848_Array[15]);
+	if (ret)
+		return ret;
+		
+
+	//restore TF, NA det setting
+//	R848_I2C.RegAddr = 0x16;
+	priv->cfg->R848_Array[14] = (priv->cfg->R848_Array[14] & 0xFE) | u1RfFlag;     
+//	R848_I2C.Data = priv->cfg->R848_Array[14];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x16, priv->cfg->R848_Array[14]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x26;
+	priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0x7F) | u1PulseFlag;  
+//	R848_I2C.Data = priv->cfg->R848_Array[30];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	    return RT_Fail;
+	ret = r848_wr(priv, 0x26, priv->cfg->R848_Array[30]);
+	if (ret)
+		return ret;
+
+	//Set NA det 710 = OFF
+//	R848_I2C.RegAddr  = 0x28;								
+	priv->cfg->R848_Array[32] = (priv->cfg->R848_Array[32] & 0xF7) | u1SPulseFlag;
+//    R848_I2C.Data = priv->cfg->R848_Array[32];
+//    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//	   return RT_Fail;
+	ret = r848_wr(priv, 0x28, priv->cfg->R848_Array[32]);
+	if (ret)
+		return ret;
+
+	return RT_Success;
+
+}
+
+
+R848_ErrCode R848_MUX( struct r848_priv *priv,u32 LO_KHz, u32 RF_KHz, R848_Standard_Type R848_Standard)
+{	
+	int ret;
+
+	R848_Freq_Info_Type Freq_Info1;
+	u8 Reg08_IMR_Gain   = 0;
+	u8 Reg09_IMR_Phase  = 0;
+	u8 Reg03_IMR_Iqcap  = 0;
+	I2C_TYPE  R848_I2C;
+	Freq_Info1 = R848_Freq_Sel(LO_KHz, RF_KHz, R848_Standard);
+
+
+	// LNA band (depend on RF_KHz)
+//	R848_I2C.RegAddr = 0x0D;	// R13[6:5] 
+	priv->cfg->R848_Array[5] = (priv->cfg->R848_Array[5] & 0x9F) | Freq_Info1.LNA_BAND;
+//	R848_I2C.Data = priv->cfg->R848_Array[5];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x0d, priv->cfg->R848_Array[5]);
+	if (ret)
+		return ret;
+
+	// RF Polyfilter
+//	R848_I2C.RegAddr = 0x21;	// R33[7:6]  
+	priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] & 0x3F) | Freq_Info1.RF_POLY;
+//	R848_I2C.Data = priv->cfg->R848_Array[25];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x21, priv->cfg->R848_Array[25]);
+	if (ret)
+		return ret;
+
+	// LNA Cap
+//	R848_I2C.RegAddr = 0x09;	// R9[7:3]  
+	priv->cfg->R848_Array[1] = (priv->cfg->R848_Array[1] & 0x07) | (Freq_Info1.LPF_CAP<<3);	
+//	R848_I2C.Data = priv->cfg->R848_Array[1];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x09, priv->cfg->R848_Array[1]);
+	if (ret)
+		return ret;
+
+	// LNA Notch
+//	R848_I2C.RegAddr = 0x0A;	// R10[4:0] 
+	priv->cfg->R848_Array[2] = (priv->cfg->R848_Array[2] & 0xE0) | (Freq_Info1.LPF_NOTCH);	
+//	R848_I2C.Data = priv->cfg->R848_Array[2];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x0a, priv->cfg->R848_Array[2]);
+	if (ret)
+		return ret;
+
+	//Set_IMR
+
+	Reg08_IMR_Gain = R848_IMR_Data[Freq_Info1.IMR_MEM].Gain_X & 0x3F;
+	Reg09_IMR_Phase = R848_IMR_Data[Freq_Info1.IMR_MEM].Phase_Y & 0x3F;
+	Reg03_IMR_Iqcap = R848_IMR_Data[Freq_Info1.IMR_MEM].Iqcap & 0x03;
+
+
+
+//	R848_I2C.RegAddr = 0x10; // R16[5:0]            
+	priv->cfg->R848_Array[8] = (priv->cfg->R848_Array[8] & 0xC0) | Reg08_IMR_Gain;
+//	R848_I2C.Data = priv->cfg->R848_Array[8];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x10, priv->cfg->R848_Array[8]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x11; // R17[5:0]  
+	priv->cfg->R848_Array[9] = (priv->cfg->R848_Array[9] & 0xC0) | Reg09_IMR_Phase;
+//	R848_I2C.Data =priv->cfg->R848_Array[9]  ;
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x11, priv->cfg->R848_Array[9]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x0B; // R11[1:0]  
+	priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xFC) | Reg03_IMR_Iqcap;
+//	R848_I2C.Data =priv->cfg->R848_Array[3]  ;
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x0b, priv->cfg->R848_Array[3]);
+	if (ret)
+		return ret;
+
+	return RT_Success;
+}
+
+
+
+
+//-----------------------------------------------------------------------------------/ 
+// Purpose: compare IMC result aray [0][1][2], find min value and store to CorArry[0]
+// input: CorArry: three IMR data array
+// output: TRUE or FALSE
+//-----------------------------------------------------------------------------------/
+R848_ErrCode R848_CompreCor( struct r848_priv *priv,R848_SectType* CorArry)
+{
+	u8 CompCunt = 0;
+	R848_SectType CorTemp;
+
+	for(CompCunt = 3;CompCunt > 0;CompCunt --)
+	{
+		if(CorArry[0].Value > CorArry[CompCunt - 1].Value) //compare IMC result [0][1][2], find min value
+		{
+			CorTemp = CorArry[0];
+			CorArry[0] = CorArry[CompCunt - 1];
+			CorArry[CompCunt - 1] = CorTemp;
+		}
+	}
+
+	return RT_Success;
+}
+
+
+//--------------------------------------------------------------------------------------------
+// Purpose: record IMC results by input gain/phase location
+//          then adjust gain or phase positive 1 step and negtive 1 step, both record results
+// input: FixPot: phase or gain
+//        FlucPot phase or gain
+//        PotReg: 0x10 or 0x11 for R848
+//        CompareTree: 3 IMR trace and results
+// output: TREU or FALSE
+//--------------------------------------------------------------------------------------------
+
+//20131217-Ryan
+
+
+R848_ErrCode R848_IQ_Tree( struct r848_priv *priv,u8 FixPot, u8 FlucPot, u8 PotReg, R848_SectType* CompareTree)
+{
+	int ret;
+	u8 TreeCunt  = 0;
+	u8 TreeTimes = 3;
+	u8 PntReg    = 0;
+	I2C_TYPE  R848_I2C;
+
+	if(PotReg == 0x10)
+		PntReg = 0x11; //phase control
+	else
+		PntReg = 0x10; //gain control
+
+	for(TreeCunt = 0;TreeCunt < TreeTimes;TreeCunt ++)
+	{
+//		R848_I2C.RegAddr = PotReg;
+//		R848_I2C.Data    = FixPot;
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			return RT_Fail;
+
+		ret = r848_wr(priv, PotReg, FixPot);
+		if (ret)
+			return ret;
+
+		//R848_I2C.RegAddr = PntReg;
+	//	R848_I2C.Data    = FlucPot;
+	//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	//		return RT_Fail;
+		ret = r848_wr(priv, PntReg, FlucPot);
+		if (ret)
+			return ret;
+
+		if(R848_Muti_Read(priv,&CompareTree[TreeCunt].Value) != RT_Success)
+			return RT_Fail;
+	
+
+		if(PotReg == 0x10)
+		{
+			CompareTree[TreeCunt].Gain_X  = FixPot;
+			CompareTree[TreeCunt].Phase_Y = FlucPot;
+		}
+		else
+		{
+			CompareTree[TreeCunt].Phase_Y  = FixPot;
+			CompareTree[TreeCunt].Gain_X = FlucPot;
+		}
+		
+		if(TreeCunt == 0)   //try right-side point
+			FlucPot ++; 
+		else if(TreeCunt == 1) //try left-side point
+		{
+			if((FlucPot & 0x1F) == 1) //if absolute location is 1, change I/Q direction
+			{
+				if(FlucPot & 0x20) //b[5]:I/Q selection. 0:Q-path, 1:I-path
+				{
+					FlucPot = (FlucPot & 0xC0) | 0x01;			
+				}
+				else
+				{
+					FlucPot = (FlucPot & 0xC0) | 0x21;
+				}
+			}
+			else
+				FlucPot = FlucPot - 2;  
+				
+		}
+	}
+
+	return RT_Success;
+}
+
+
+R848_ErrCode R848_Section( struct r848_priv *priv,R848_SectType* IQ_Pont)
+{
+	R848_SectType Compare_IQ[3];
+	R848_SectType Compare_Bet[3];
+
+	//Try X-1 column and save min result to Compare_Bet[0]
+	if((IQ_Pont->Gain_X & 0x1F) == 0x00)
+	{
+		Compare_IQ[0].Gain_X = ((IQ_Pont->Gain_X) & 0xDF) + 1;  //Q-path, Gain=1
+	}
+	else
+	{
+		Compare_IQ[0].Gain_X  = IQ_Pont->Gain_X - 1;  //left point
+	}
+	Compare_IQ[0].Phase_Y = IQ_Pont->Phase_Y;
+
+	if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success)  // y-direction
+		return RT_Fail;		
+
+	if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		return RT_Fail;
+
+	Compare_Bet[0].Gain_X = Compare_IQ[0].Gain_X;
+	Compare_Bet[0].Phase_Y = Compare_IQ[0].Phase_Y;
+	Compare_Bet[0].Value = Compare_IQ[0].Value;
+
+	//Try X column and save min result to Compare_Bet[1]
+	Compare_IQ[0].Gain_X = IQ_Pont->Gain_X;
+	Compare_IQ[0].Phase_Y = IQ_Pont->Phase_Y;
+
+	if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success)
+		return RT_Fail;	
+
+	if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		return RT_Fail;
+
+	Compare_Bet[1].Gain_X = Compare_IQ[0].Gain_X;
+	Compare_Bet[1].Phase_Y = Compare_IQ[0].Phase_Y;
+	Compare_Bet[1].Value = Compare_IQ[0].Value;
+
+	//Try X+1 column and save min result to Compare_Bet[2]
+	if((IQ_Pont->Gain_X & 0x1F) == 0x00)		
+		Compare_IQ[0].Gain_X = ((IQ_Pont->Gain_X) | 0x20) + 1;  //I-path, Gain=1
+	else
+	    Compare_IQ[0].Gain_X = IQ_Pont->Gain_X + 1;
+	Compare_IQ[0].Phase_Y = IQ_Pont->Phase_Y;
+
+	if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success)
+		return RT_Fail;		
+
+	if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		return RT_Fail;
+
+	Compare_Bet[2].Gain_X = Compare_IQ[0].Gain_X;
+	Compare_Bet[2].Phase_Y = Compare_IQ[0].Phase_Y;
+	Compare_Bet[2].Value = Compare_IQ[0].Value;
+
+	if(R848_CompreCor(priv,&Compare_Bet[0]) != RT_Success)
+		return RT_Fail;
+
+	*IQ_Pont = Compare_Bet[0];
+	
+	return RT_Success;
+}
+
+R848_ErrCode R848_IMR_Cross( struct r848_priv *priv,R848_SectType* IQ_Pont, u8* X_Direct)
+{
+	int ret;
+
+	R848_SectType Compare_Cross[9]; //(0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0)+(0,Q-2)(0,I-2)(Q-2,0)(I-2,0)
+	R848_SectType Compare_Temp;
+	u8 CrossCount = 0;
+	u8 Reg16 = priv->cfg->R848_Array[8] & 0xC0;
+	u8 Reg17 = priv->cfg->R848_Array[9] & 0xC0;
+	I2C_TYPE  R848_I2C;
+
+	memset(&Compare_Temp, 0, sizeof(R848_SectType));
+	Compare_Temp.Value = 255;
+
+	for(CrossCount=0; CrossCount<9; CrossCount++)
+	{
+
+		if(CrossCount==0)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16;
+		  Compare_Cross[CrossCount].Phase_Y = Reg17;
+		}
+		else if(CrossCount==1)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16;       //0
+		  Compare_Cross[CrossCount].Phase_Y = Reg17 + 1;  //Q-1
+		}
+		else if(CrossCount==2)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16;               //0
+		  Compare_Cross[CrossCount].Phase_Y = (Reg17 | 0x20) + 1; //I-1
+		}
+		else if(CrossCount==3)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16 + 1; //Q-1
+		  Compare_Cross[CrossCount].Phase_Y = Reg17;
+		}
+		else if(CrossCount==4)
+		{
+		  Compare_Cross[CrossCount].Gain_X = (Reg16 | 0x20) + 1; //I-1
+		  Compare_Cross[CrossCount].Phase_Y = Reg17;
+		}
+		else if(CrossCount==5)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16;       //0
+		  Compare_Cross[CrossCount].Phase_Y = Reg17 + 2;  //Q-2
+		}
+		else if(CrossCount==6)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16;               //0
+		  Compare_Cross[CrossCount].Phase_Y = (Reg17 | 0x20) + 2; //I-2
+		}
+		else if(CrossCount==7)
+		{
+		  Compare_Cross[CrossCount].Gain_X = Reg16 + 2; //Q-2
+		  Compare_Cross[CrossCount].Phase_Y = Reg17;
+		}
+		else if(CrossCount==8)
+		{
+		  Compare_Cross[CrossCount].Gain_X = (Reg16 | 0x20) + 2; //I-2
+		  Compare_Cross[CrossCount].Phase_Y = Reg17;
+		}
+
+//    	R848_I2C.RegAddr = 0x10;	
+//	    R848_I2C.Data    = Compare_Cross[CrossCount].Gain_X;
+//	    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		   return RT_Fail;
+	ret = r848_wr(priv, 0x10, Compare_Cross[CrossCount].Gain_X);
+	if (ret)
+		return ret;
+
+//	    R848_I2C.RegAddr = 0x11;	
+//	    R848_I2C.Data    = Compare_Cross[CrossCount].Phase_Y;
+//	    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		  return RT_Fail;
+	ret = r848_wr(priv, 0x11, Compare_Cross[CrossCount].Phase_Y);
+	if (ret)
+		return ret;
+	
+        if(R848_Muti_Read(priv,&Compare_Cross[CrossCount].Value) != RT_Success)
+		  return RT_Fail;
+
+		if( Compare_Cross[CrossCount].Value < Compare_Temp.Value)
+		{
+		  Compare_Temp.Value = Compare_Cross[CrossCount].Value;
+		  Compare_Temp.Gain_X = Compare_Cross[CrossCount].Gain_X;
+		  Compare_Temp.Phase_Y = Compare_Cross[CrossCount].Phase_Y;		
+		}
+	} //end for loop
+
+
+    if(((Compare_Temp.Phase_Y & 0x3F)==0x01) || (Compare_Temp.Phase_Y & 0x3F)==0x02)  //phase Q1 or Q2
+	{
+      *X_Direct = (u8) 0;
+	  IQ_Pont[0].Gain_X = Compare_Cross[0].Gain_X;    //0
+	  IQ_Pont[0].Phase_Y = Compare_Cross[0].Phase_Y; //0
+	  IQ_Pont[0].Value = Compare_Cross[0].Value;
+
+	  IQ_Pont[1].Gain_X = Compare_Cross[1].Gain_X;    //0
+	  IQ_Pont[1].Phase_Y = Compare_Cross[1].Phase_Y; //Q1
+	  IQ_Pont[1].Value = Compare_Cross[1].Value;
+
+	  IQ_Pont[2].Gain_X = Compare_Cross[5].Gain_X;   //0
+	  IQ_Pont[2].Phase_Y = Compare_Cross[5].Phase_Y;//Q2
+	  IQ_Pont[2].Value = Compare_Cross[5].Value;
+	}
+	else if(((Compare_Temp.Phase_Y & 0x3F)==0x21) || (Compare_Temp.Phase_Y & 0x3F)==0x22)  //phase I1 or I2
+	{
+      *X_Direct = (u8) 0;
+	  IQ_Pont[0].Gain_X = Compare_Cross[0].Gain_X;    //0
+	  IQ_Pont[0].Phase_Y = Compare_Cross[0].Phase_Y; //0
+	  IQ_Pont[0].Value = Compare_Cross[0].Value;
+
+	  IQ_Pont[1].Gain_X = Compare_Cross[2].Gain_X;    //0
+	  IQ_Pont[1].Phase_Y = Compare_Cross[2].Phase_Y; //Q1
+	  IQ_Pont[1].Value = Compare_Cross[2].Value;
+
+	  IQ_Pont[2].Gain_X = Compare_Cross[6].Gain_X;   //0
+	  IQ_Pont[2].Phase_Y = Compare_Cross[6].Phase_Y;//Q2
+	  IQ_Pont[2].Value = Compare_Cross[6].Value;
+	}
+	else if(((Compare_Temp.Gain_X & 0x3F)==0x01) || (Compare_Temp.Gain_X & 0x3F)==0x02)  //gain Q1 or Q2
+	{
+      *X_Direct = (u8) 1;
+	  IQ_Pont[0].Gain_X = Compare_Cross[0].Gain_X;    //0
+	  IQ_Pont[0].Phase_Y = Compare_Cross[0].Phase_Y; //0
+	  IQ_Pont[0].Value = Compare_Cross[0].Value;
+
+	  IQ_Pont[1].Gain_X = Compare_Cross[3].Gain_X;    //Q1
+	  IQ_Pont[1].Phase_Y = Compare_Cross[3].Phase_Y; //0
+	  IQ_Pont[1].Value = Compare_Cross[3].Value;
+
+	  IQ_Pont[2].Gain_X = Compare_Cross[7].Gain_X;   //Q2
+	  IQ_Pont[2].Phase_Y = Compare_Cross[7].Phase_Y;//0
+	  IQ_Pont[2].Value = Compare_Cross[7].Value;
+	}
+	else if(((Compare_Temp.Gain_X & 0x3F)==0x21) || (Compare_Temp.Gain_X & 0x3F)==0x22)  //gain I1 or I2
+	{
+      *X_Direct = (u8) 1;
+	  IQ_Pont[0].Gain_X = Compare_Cross[0].Gain_X;    //0
+	  IQ_Pont[0].Phase_Y = Compare_Cross[0].Phase_Y; //0
+	  IQ_Pont[0].Value = Compare_Cross[0].Value;
+
+	  IQ_Pont[1].Gain_X = Compare_Cross[4].Gain_X;    //I1
+	  IQ_Pont[1].Phase_Y = Compare_Cross[4].Phase_Y; //0
+	  IQ_Pont[1].Value = Compare_Cross[4].Value;
+
+	  IQ_Pont[2].Gain_X = Compare_Cross[8].Gain_X;   //I2
+	  IQ_Pont[2].Phase_Y = Compare_Cross[8].Phase_Y;//0
+	  IQ_Pont[2].Value = Compare_Cross[8].Value;
+	}
+	else //(0,0) 
+	{	
+	  *X_Direct = (u8) 1;
+	  IQ_Pont[0].Gain_X = Compare_Cross[0].Gain_X;
+	  IQ_Pont[0].Phase_Y = Compare_Cross[0].Phase_Y;
+	  IQ_Pont[0].Value = Compare_Cross[0].Value;
+
+	  IQ_Pont[1].Gain_X = Compare_Cross[3].Gain_X;    //Q1
+	  IQ_Pont[1].Phase_Y = Compare_Cross[3].Phase_Y; //0
+	  IQ_Pont[1].Value = Compare_Cross[3].Value;
+
+	  IQ_Pont[2].Gain_X = Compare_Cross[4].Gain_X;   //I1
+	  IQ_Pont[2].Phase_Y = Compare_Cross[4].Phase_Y; //0
+	  IQ_Pont[2].Value = Compare_Cross[4].Value;
+	}
+	return RT_Success;
+}
+
+//-------------------------------------------------------------------------------------//
+// Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare with min value
+//          new < min => update to min and continue
+//          new > min => Exit
+// input: StepArry: three IMR data array
+//        Pace: gain or phase register
+// output: TRUE or FALSE 
+//-------------------------------------------------------------------------------------//
+R848_ErrCode R848_CompreStep( struct r848_priv *priv,R848_SectType* StepArry, u8 Pace)
+{
+	int ret;
+	R848_SectType StepTemp;
+	I2C_TYPE  R848_I2C;
+	//min value already saved in StepArry[0]
+	StepTemp.Phase_Y = StepArry[0].Phase_Y;
+	StepTemp.Gain_X  = StepArry[0].Gain_X;
+	//StepTemp.Iqcap  = StepArry[0].Iqcap;
+
+	while(((StepTemp.Gain_X & 0x1F) < R848_IMR_TRIAL) && ((StepTemp.Phase_Y & 0x1F) < R848_IMR_TRIAL))  
+	{
+		if(Pace == 0x10)	
+			StepTemp.Gain_X ++;
+		else
+			StepTemp.Phase_Y ++;
+	
+//		R848_I2C.RegAddr = 0x10;	
+//		R848_I2C.Data    = StepTemp.Gain_X ;
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			return RT_Fail;
+		ret = r848_wr(priv, 0x10, StepTemp.Gain_X);
+		if (ret)
+			return ret;
+
+//		R848_I2C.RegAddr = 0x11;	
+//		R848_I2C.Data    = StepTemp.Phase_Y;
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			return RT_Fail;
+		ret = r848_wr(priv, 0x11, StepTemp.Phase_Y);
+		if (ret)
+			return ret;
+
+		if(R848_Muti_Read(priv,&StepTemp.Value) != RT_Success)
+			return RT_Fail;
+
+		if(StepTemp.Value <= StepArry[0].Value)
+		{
+			StepArry[0].Gain_X  = StepTemp.Gain_X;
+			StepArry[0].Phase_Y = StepTemp.Phase_Y;
+			//StepArry[0].Iqcap = StepTemp.Iqcap;
+			StepArry[0].Value   = StepTemp.Value;
+		}
+		else if((StepTemp.Value - 2) > StepArry[0].Value)
+		{
+			break;		
+		}
+		
+	} //end of while()
+	
+	return RT_Success;
+}
+
+R848_ErrCode R848_IMR_Iqcap( struct r848_priv *priv,R848_SectType* IQ_Point)   
+{
+    R848_SectType Compare_Temp;
+	int i = 0, ret;
+	I2C_TYPE  R848_I2C;
+
+	//Set Gain/Phase to right setting
+//	R848_I2C.RegAddr = 0x10;	// R16[5:0]  
+//	R848_I2C.Data = IQ_Point->Gain_X; 
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x10, IQ_Point->Gain_X);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x11;	// R17[5:0]  
+//	R848_I2C.Data = IQ_Point->Phase_Y;
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x11, IQ_Point->Phase_Y);
+	if (ret)
+		return ret;
+
+	//try iqcap
+	for(i=0; i<3; i++)	
+	{
+		Compare_Temp.Iqcap = (u8) i;  
+//		R848_I2C.RegAddr = 0x0B;		// R11[1:0] 
+		priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xFC) | Compare_Temp.Iqcap;  
+//		R848_I2C.Data = priv->cfg->R848_Array[3];  
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			   return RT_Fail;
+		ret = r848_wr(priv, 0x0b, priv->cfg->R848_Array[3]);
+		if (ret)
+			return ret;
+
+		if(R848_Muti_Read(priv,&(Compare_Temp.Value)) != RT_Success)
+			   return RT_Fail;
+
+		if(Compare_Temp.Value < IQ_Point->Value)
+		{
+			IQ_Point->Value = Compare_Temp.Value; 
+			IQ_Point->Iqcap = Compare_Temp.Iqcap;
+		}
+	}
+
+    return RT_Success;
+}
+
+
+R848_ErrCode R848_IQ( struct r848_priv *priv,R848_SectType* IQ_Pont)
+{
+	int ret;
+	R848_SectType Compare_IQ[3];
+	u8   VGA_Count = 0;
+	u8   VGA_Read = 0;
+	u8   X_Direction;  // 1:X, 0:Y
+	I2C_TYPE  R848_I2C;	
+
+
+	// increase VGA power to let image significant
+	for(VGA_Count=11; VGA_Count < 16; VGA_Count ++)
+	{
+//		R848_I2C.RegAddr = 0x14; // R848:R20[3:0]  
+//		R848_I2C.Data    = (priv->cfg->R848_Array[12] & 0xF0) + VGA_Count;  
+//		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//			return RT_Fail;
+		ret = r848_wr(priv, 0x14, (priv->cfg->R848_Array[12] & 0xF0) + VGA_Count);
+		if (ret)
+			return ret;
+
+		msleep(10); //
+		
+		if(R848_Muti_Read(priv,&VGA_Read) != RT_Success)
+			return RT_Fail;
+
+		if(VGA_Read > 40)
+			break;
+	}
+
+	Compare_IQ[0].Gain_X  = priv->cfg->R848_Array[8] & 0xC0; // R16[5:0]  
+	Compare_IQ[0].Phase_Y = priv->cfg->R848_Array[9] & 0xC0; // R17[5:0] 
+	//Compare_IQ[0].Iqcap = R848_iniArray[3] & 0xFC;
+
+	    // Determine X or Y
+	    if(R848_IMR_Cross(priv,&Compare_IQ[0], &X_Direction) != RT_Success)
+			return RT_Fail;
+
+		if(X_Direction==1)
+		{
+			//compare and find min of 3 points. determine I/Q direction
+		    if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+			  return RT_Fail;
+
+		    //increase step to find min value of this direction
+		    if(R848_CompreStep(priv,&Compare_IQ[0], 0x10) != RT_Success)  //X
+			  return RT_Fail;	
+		}
+		else
+		{
+		   //compare and find min of 3 points. determine I/Q direction
+		   if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		   	 return RT_Fail;
+
+		   //increase step to find min value of this direction
+		   if(R848_CompreStep(priv,&Compare_IQ[0], 0x11) != RT_Success)  //Y
+			 return RT_Fail;	
+		}
+
+		//Another direction
+		if(X_Direction==1)
+		{	    
+           if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success) //Y	
+		     return RT_Fail;	
+
+		   //compare and find min of 3 points. determine I/Q direction
+		   if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		   	 return RT_Fail;
+
+		   //increase step to find min value of this direction
+		   if(R848_CompreStep(priv,&Compare_IQ[0], 0x11) != RT_Success)  //Y
+			 return RT_Fail;	
+		}
+		else
+		{
+		   if(R848_IQ_Tree(priv,Compare_IQ[0].Phase_Y, Compare_IQ[0].Gain_X, 0x11, &Compare_IQ[0]) != RT_Success) //X
+		     return RT_Fail;	
+        
+		   //compare and find min of 3 points. determine I/Q direction
+		   if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		     return RT_Fail;
+
+	       //increase step to find min value of this direction
+		   if(R848_CompreStep(priv,&Compare_IQ[0], 0x10) != RT_Success) //X
+		     return RT_Fail;	
+		}
+		
+
+		//--- Check 3 points again---//
+		if(X_Direction==1)
+		{
+		    if(R848_IQ_Tree(priv,Compare_IQ[0].Phase_Y, Compare_IQ[0].Gain_X, 0x11, &Compare_IQ[0]) != RT_Success) //X
+			  return RT_Fail;	
+		}
+		else
+		{
+		   if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success) //Y
+			return RT_Fail;		
+		}
+
+		if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+			return RT_Fail;
+
+    //Section-9 check
+    //if(R848_F_IMR(&Compare_IQ[0]) != RT_Success)
+	if(R848_Section(priv,&Compare_IQ[0]) != RT_Success)
+			return RT_Fail;
+
+	//clear IQ_Cap = 0   //  R11[1:0]  
+	Compare_IQ[0].Iqcap = priv->cfg->R848_Array[3] & 0xFC;
+
+	if(R848_IMR_Iqcap(priv,&Compare_IQ[0]) != RT_Success)
+			return RT_Fail;
+
+	*IQ_Pont = Compare_IQ[0];
+
+	//reset gain/phase/iqcap control setting
+//	R848_I2C.RegAddr = 0x10;	// R16[5:0]  
+	priv->cfg->R848_Array[8] = priv->cfg->R848_Array[8] & 0xC0;
+//	R848_I2C.Data = priv->cfg->R848_Array[8];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x10, priv->cfg->R848_Array[8]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x11;	// R17[5:0]  
+	priv->cfg->R848_Array[9] = priv->cfg->R848_Array[9] & 0xC0;
+//	R848_I2C.Data = priv->cfg->R848_Array[9];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x11, priv->cfg->R848_Array[9]);
+	if (ret)
+		return ret;
+
+//	R848_I2C.RegAddr = 0x0B;	//  R11[1:0] 
+	priv->cfg->R848_Array[3] = priv->cfg->R848_Array[3] & 0xFC;
+//	R848_I2C.Data = priv->cfg->R848_Array[3];
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x0b, priv->cfg->R848_Array[3]);
+	if (ret)
+		return ret;
+
+	return RT_Success;
+}
+
+//----------------------------------------------------------------------------------------//
+// purpose: search surrounding points from previous point 
+//          try (x-1), (x), (x+1) columns, and find min IMR result point
+// input: IQ_Pont: previous point data(IMR Gain, Phase, ADC Result, RefRreq)
+//                 will be updated to final best point                 
+// output: TRUE or FALSE
+//----------------------------------------------------------------------------------------//
+R848_ErrCode R848_F_IMR( struct r848_priv *priv,R848_SectType* IQ_Pont)
+{
+	int ret;
+	R848_SectType Compare_IQ[3];
+	R848_SectType Compare_Bet[3];
+	u8 VGA_Count = 0;
+	u8 VGA_Read = 0;
+	I2C_TYPE  R848_I2C;
+
+	//VGA
+	for(VGA_Count=11; VGA_Count < 16; VGA_Count ++)
+	{
+//		R848_I2C.RegAddr = 0x14;	//  R20[3:0]  
+//        R848_I2C.Data    = (priv->cfg->R848_Array[12] & 0xF0) + VGA_Count;
+//		if(I2C_Write(priv, &R848_I2C) != RT_Success)
+//			return RT_Fail;
+		ret = r848_wr(priv, 0x14, (priv->cfg->R848_Array[12] & 0xF0) + VGA_Count);
+		if (ret)
+			return ret;
+
+		msleep(10);
+		
+		if(R848_Muti_Read(priv,&VGA_Read) != RT_Success)
+			return RT_Fail;
+
+		if(VGA_Read > 40)
+		break;
+	}
+
+	//Try X-1 column and save min result to Compare_Bet[0]
+	if((IQ_Pont->Gain_X & 0x1F) == 0x00)
+	{
+		Compare_IQ[0].Gain_X = ((IQ_Pont->Gain_X) & 0xDF) + 1;  //Q-path, Gain=1
+	}
+	else
+	{
+		Compare_IQ[0].Gain_X  = IQ_Pont->Gain_X - 1;  //left point
+	}
+	Compare_IQ[0].Phase_Y = IQ_Pont->Phase_Y;
+
+	if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success)  // y-direction
+		return RT_Fail;	
+
+	if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		return RT_Fail;
+
+	Compare_Bet[0].Gain_X = Compare_IQ[0].Gain_X;
+	Compare_Bet[0].Phase_Y = Compare_IQ[0].Phase_Y;
+	Compare_Bet[0].Value = Compare_IQ[0].Value;
+
+	//Try X column and save min result to Compare_Bet[1]
+	Compare_IQ[0].Gain_X = IQ_Pont->Gain_X;
+	Compare_IQ[0].Phase_Y = IQ_Pont->Phase_Y;
+
+	if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success)
+		return RT_Fail;	
+
+	if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		return RT_Fail;
+
+	Compare_Bet[1].Gain_X = Compare_IQ[0].Gain_X;
+	Compare_Bet[1].Phase_Y = Compare_IQ[0].Phase_Y;
+	Compare_Bet[1].Value = Compare_IQ[0].Value;
+
+	//Try X+1 column and save min result to Compare_Bet[2]
+	if((IQ_Pont->Gain_X & 0x1F) == 0x00)		
+		Compare_IQ[0].Gain_X = ((IQ_Pont->Gain_X) | 0x20) + 1;  //I-path, Gain=1
+	else
+	    Compare_IQ[0].Gain_X = IQ_Pont->Gain_X + 1;
+	Compare_IQ[0].Phase_Y = IQ_Pont->Phase_Y;
+
+	if(R848_IQ_Tree(priv,Compare_IQ[0].Gain_X, Compare_IQ[0].Phase_Y, 0x10, &Compare_IQ[0]) != RT_Success)
+		return RT_Fail;		
+
+	if(R848_CompreCor(priv,&Compare_IQ[0]) != RT_Success)
+		return RT_Fail;
+
+	Compare_Bet[2].Gain_X = Compare_IQ[0].Gain_X;
+	Compare_Bet[2].Phase_Y = Compare_IQ[0].Phase_Y;
+	Compare_Bet[2].Value = Compare_IQ[0].Value;
+
+	if(R848_CompreCor(priv,&Compare_Bet[0]) != RT_Success)
+		return RT_Fail;
+
+	//clear IQ_Cap = 0
+	Compare_Bet[0].Iqcap = priv->cfg->R848_Array[3] & 0xFC;	//  R11[1:0] 
+
+	if(R848_IMR_Iqcap(priv,&Compare_Bet[0]) != RT_Success)
+		return RT_Fail;
+
+	*IQ_Pont = Compare_Bet[0];
+	
+	return RT_Success;
+}
+
+
+R848_ErrCode R848_SetTF( struct r848_priv *priv,u32 u4FreqKHz, u8 u1TfType)
+{
+	int ret;
+    u8    u1FreqCount = 0;
+	u32   u4Freq1 = 0;
+	u32   u4Freq2 = 0;
+	u32   u4Ratio;
+	u8    u1TF_Set_Result1 = 0;
+	u8    u1TF_Set_Result2 = 0;
+	u8    u1TF_tmp1, u1TF_tmp2;
+	u8    u1TFCalNum = R848_TF_HIGH_NUM;
+	I2C_TYPE  R848_I2C;
+	u8  R848_TF = 0;
+
+	if(u4FreqKHz<R848_LNA_LOW_LOWEST[R848_TF_BEAD])  //Ultra Low
+	{
+		 u1TFCalNum = R848_TF_LOWEST_NUM;
+         while((u4FreqKHz < R848_TF_Freq_Lowest[u1TfType][u1FreqCount]) && (u1FreqCount<R848_TF_LOWEST_NUM))
+		 {
+            u1FreqCount++;
+		 }
+
+		 if(u1FreqCount==0)
+		 {
+			 R848_TF = R848_TF_Result_Lowest[u1TfType][0];
+		 }
+		 else if(u1FreqCount==R848_TF_LOWEST_NUM)
+         {
+			 R848_TF = R848_TF_Result_Lowest[u1TfType][R848_TF_LOWEST_NUM-1];
+		 }
+		 else
+		 {
+			 u1TF_Set_Result1 = R848_TF_Result_Lowest[u1TfType][u1FreqCount-1]; 
+		     u1TF_Set_Result2 = R848_TF_Result_Lowest[u1TfType][u1FreqCount]; 
+		     u4Freq1 = R848_TF_Freq_Lowest[u1TfType][u1FreqCount-1];
+		     u4Freq2 = R848_TF_Freq_Lowest[u1TfType][u1FreqCount]; 
+
+			 //u4Ratio = (u4Freq1- u4FreqKHz)*100/(u4Freq1 - u4Freq2);
+             //R848_TF = u1TF_Set_Result1 + (u8)((u1TF_Set_Result2 - u1TF_Set_Result1)*u4Ratio/100);
+
+			 u1TF_tmp1 = ((u1TF_Set_Result1 & 0x40)>>2)*3 + (u1TF_Set_Result1 & 0x3F);  //b6 is 3xb4
+			 u1TF_tmp2 = ((u1TF_Set_Result2 & 0x40)>>2)*3 + (u1TF_Set_Result2 & 0x3F);			 
+			 u4Ratio = (u4Freq1- u4FreqKHz)*100/(u4Freq1 - u4Freq2);
+			 R848_TF = u1TF_tmp1 + (u8)((u1TF_tmp2 - u1TF_tmp1)*u4Ratio/100);
+			 if(R848_TF>=0x40)
+				 R848_TF = (R848_TF + 0x10);
+
+		 }
+	}
+	else if((u4FreqKHz>=R848_LNA_LOW_LOWEST[R848_TF_BEAD]) && (u4FreqKHz<R848_LNA_MID_LOW[R848_TF_BEAD]))  //Low
+	{
+		 u1TFCalNum = R848_TF_LOW_NUM;
+         while((u4FreqKHz < R848_TF_Freq_Low[u1TfType][u1FreqCount]) && (u1FreqCount<R848_TF_LOW_NUM))
+		 {
+            u1FreqCount++;
+		 }
+
+		 if(u1FreqCount==0)
+		 {
+			 R848_TF = R848_TF_Result_Low[u1TfType][0];
+		 }
+		 else if(u1FreqCount==R848_TF_LOW_NUM)
+        {
+			 R848_TF = R848_TF_Result_Low[u1TfType][R848_TF_LOW_NUM-1];
+		 }
+		 else
+		 {
+			 u1TF_Set_Result1 = R848_TF_Result_Low[u1TfType][u1FreqCount-1]; 
+		     u1TF_Set_Result2 = R848_TF_Result_Low[u1TfType][u1FreqCount]; 
+		     u4Freq1 = R848_TF_Freq_Low[u1TfType][u1FreqCount-1];
+		     u4Freq2 = R848_TF_Freq_Low[u1TfType][u1FreqCount]; 
+
+			 //u4Ratio = (u4Freq1- u4FreqKHz)*100/(u4Freq1 - u4Freq2);
+             //R848_TF = u1TF_Set_Result1 + (u8)((u1TF_Set_Result2 - u1TF_Set_Result1)*u4Ratio/100);
+
+			 u1TF_tmp1 = ((u1TF_Set_Result1 & 0x40)>>2) + (u1TF_Set_Result1 & 0x3F);  //b6 is 1xb4
+			 u1TF_tmp2 = ((u1TF_Set_Result2 & 0x40)>>2) + (u1TF_Set_Result2 & 0x3F);			 
+			 u4Ratio = (u4Freq1- u4FreqKHz)*100/(u4Freq1 - u4Freq2);
+			 R848_TF = u1TF_tmp1 + (u8)((u1TF_tmp2 - u1TF_tmp1)*u4Ratio/100);
+			 if(R848_TF>=0x40)
+				 R848_TF = (R848_TF + 0x30);
+		 }
+	}
+	else if((u4FreqKHz>=R848_LNA_MID_LOW[R848_TF_BEAD]) && (u4FreqKHz<R848_LNA_HIGH_MID[R848_TF_BEAD]))  //Mid
+    {
+		 u1TFCalNum = R848_TF_MID_NUM;
+         while((u4FreqKHz < R848_TF_Freq_Mid[u1TfType][u1FreqCount]) && (u1FreqCount<R848_TF_MID_NUM))
+		 {
+            u1FreqCount++;
+		 }
+
+		 if(u1FreqCount==0)
+		 {
+			 R848_TF = R848_TF_Result_Mid[u1TfType][0];
+		 }
+		 else if(u1FreqCount==R848_TF_MID_NUM)
+        {
+			 R848_TF = R848_TF_Result_Mid[u1TfType][R848_TF_MID_NUM-1];
+		 }
+		 else
+		 {
+			 u1TF_Set_Result1 = R848_TF_Result_Mid[u1TfType][u1FreqCount-1]; 
+		     u1TF_Set_Result2 = R848_TF_Result_Mid[u1TfType][u1FreqCount]; 
+		     u4Freq1 = R848_TF_Freq_Mid[u1TfType][u1FreqCount-1];
+		     u4Freq2 = R848_TF_Freq_Mid[u1TfType][u1FreqCount]; 
+			 u4Ratio = (u4Freq1- u4FreqKHz)*100/(u4Freq1 - u4Freq2);
+             R848_TF = u1TF_Set_Result1 + (u8)((u1TF_Set_Result2 - u1TF_Set_Result1)*u4Ratio/100);
+		 }
+	}
+	else  //HIGH
+	{
+		 u1TFCalNum = R848_TF_HIGH_NUM;
+         while((u4FreqKHz < R848_TF_Freq_High[u1TfType][u1FreqCount]) && (u1FreqCount<R848_TF_HIGH_NUM))
+		 {
+            u1FreqCount++;
+		 }
+
+		 if(u1FreqCount==0)
+		 {
+			 R848_TF = R848_TF_Result_High[u1TfType][0];
+		 }
+		 else if(u1FreqCount==R848_TF_HIGH_NUM)
+        {
+			 R848_TF = R848_TF_Result_High[u1TfType][R848_TF_HIGH_NUM-1];
+		 }
+		 else
+		 {
+			 u1TF_Set_Result1 = R848_TF_Result_High[u1TfType][u1FreqCount-1]; 
+		     u1TF_Set_Result2 = R848_TF_Result_High[u1TfType][u1FreqCount]; 
+		     u4Freq1 = R848_TF_Freq_High[u1TfType][u1FreqCount-1];
+		     u4Freq2 = R848_TF_Freq_High[u1TfType][u1FreqCount]; 
+			 u4Ratio = (u4Freq1- u4FreqKHz)*100/(u4Freq1 - u4Freq2);
+             R848_TF = u1TF_Set_Result1 + (u8)((u1TF_Set_Result2 - u1TF_Set_Result1)*u4Ratio/100);
+		 }
+	}
+  
+	// R8[6:0] 
+//	R848_I2C.RegAddr = 0x08;
+	priv->cfg->R848_Array[0] = (priv->cfg->R848_Array[0] & 0x80) | R848_TF;
+//	R848_I2C.Data = priv->cfg->R848_Array[0]  ;
+//	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+//		return RT_Fail;
+	ret = r848_wr(priv, 0x0b, priv->cfg->R848_Array[0]);
+	if (ret)
+		return ret;
+
+    return RT_Success;
+}
+
+R848_ErrCode R848_IMR( struct r848_priv *priv,u8 IMR_MEM, bool IM_Flag)
+{
+	u32 RingVCO = 0;
+	u32 RingFreq = 0;
+	u8  u1MixerGain = 8;
+ 	I2C_TYPE  R848_I2C;
+
+	R848_SectType IMR_POINT;
+
+	RingVCO = 3200000;
+	priv->cfg->R848_Array[31] &= 0x3F;   //clear ring_div1, R24[7:6]	//R848:R39[7:6]  39-8=31  39(0x27) is addr ; [31] is data 
+	priv->cfg->R848_Array[25] &= 0xFC;   //clear ring_div2, R25[1:0]	//R848:R33[1:0]  33-8=25  33(0x21) is addr ; [25] is data 
+	priv->cfg->R848_Array[25] &= 0xDF;   //clear vco_band, R25[5]		//R848:R33[5]    33-8=25  33(0x21) is addr ; [25] is data 
+	priv->cfg->R848_Array[31] &= 0xC3;   //clear ring_div_num, R24[3:0]//R848:R39[5:2]  39-8=31  39(0x27) is addr ; [31] is data
+
+	switch(IMR_MEM)
+	{
+	case 0: // RingFreq = 66.66M
+		RingFreq = RingVCO/48;
+		priv->cfg->R848_Array[31] |= 0x80;  // ring_div1 /6 (2)
+		priv->cfg->R848_Array[25] |= 0x03;  // ring_div2 /8 (3)		
+		priv->cfg->R848_Array[25] |= 0x00;  // vco_band = 0 (high)
+        priv->cfg->R848_Array[31] |= 0x24;  // ring_div_num = 9
+		u1MixerGain = 8;
+		break;
+	case 1: // RingFreq = 200M
+		RingFreq = RingVCO/16;
+		priv->cfg->R848_Array[31] |= 0x00;  // ring_div1 /4 (0)
+		priv->cfg->R848_Array[25] |= 0x02;  // ring_div2 /4 (2)		
+		priv->cfg->R848_Array[25] |= 0x00;  // vco_band = 0 (high)
+        priv->cfg->R848_Array[31] |= 0x24;  // ring_div_num = 9
+		u1MixerGain = 6;
+		break;
+	case 2: // RingFreq = 400M
+		RingFreq = RingVCO/8;
+		priv->cfg->R848_Array[31] |= 0x00;  // ring_div1 /4 (0)
+		priv->cfg->R848_Array[25] |= 0x01;  // ring_div2 /2 (1)		
+		priv->cfg->R848_Array[25] |= 0x00;  // vco_band = 0 (high)
+        priv->cfg->R848_Array[31] |= 0x24;  // ring_div_num = 9
+		u1MixerGain = 6;
+		break;
+	case 3: // RingFreq = 533.33M
+		RingFreq = RingVCO/6;
+		priv->cfg->R848_Array[31] |= 0x80;  // ring_div1 /6 (2)
+		priv->cfg->R848_Array[25] |= 0x00;  // ring_div2 /1 (0)		
+		priv->cfg->R848_Array[25] |= 0x00;  // vco_band = 0 (high)
+        priv->cfg->R848_Array[31] |= 0x24;  // ring_div_num = 9
+		u1MixerGain = 8;
+		break;
+	case 4: // RingFreq = 800M
+		RingFreq = RingVCO/4;
+		priv->cfg->R848_Array[31] |= 0x00;  // ring_div1 /4 (0)
+		priv->cfg->R848_Array[25] |= 0x00;  // ring_div2 /1 (0)		
+		priv->cfg->R848_Array[25] |= 0x00;  // vco_band = 0 (high)
+        priv->cfg->R848_Array[31] |= 0x24;  // ring_div_num = 9
+		u1MixerGain = 8;
+		break;
+	default:
+		RingFreq = RingVCO/4;
+		priv->cfg->R848_Array[31] |= 0x00;  // ring_div1 /4 (0)
+		priv->cfg->R848_Array[25] |= 0x00;  // ring_div2 /1 (0)		
+		priv->cfg->R848_Array[25] |= 0x00;  // vco_band = 0 (high)
+        priv->cfg->R848_Array[31] |= 0x24;  // ring_div_num = 9
+		u1MixerGain = 8;
+		break;
+	}
+
+	//Mixer Amp Gain
+	R848_I2C.RegAddr = 0x0F;	//R848:R15[4:0] 
+	priv->cfg->R848_Array[7] = (priv->cfg->R848_Array[7] & 0xE0) | u1MixerGain; 
+    R848_I2C.Data = priv->cfg->R848_Array[7];
+    if(I2C_Write(priv,&R848_I2C) != RT_Success)
+        return RT_Fail;
+
+	//write I2C to set RingPLL
+	R848_I2C.RegAddr = 0x27;
+	R848_I2C.Data    = priv->cfg->R848_Array[31];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+	
+	R848_I2C.RegAddr = 0x21;
+	R848_I2C.Data    = priv->cfg->R848_Array[25];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	//Ring PLL power
+	//if((RingFreq>=0) && (RingFreq<R848_RING_POWER_FREQ_LOW))
+	if(((RingFreq<R848_RING_POWER_FREQ_LOW)||(RingFreq>R848_RING_POWER_FREQ_HIGH)))  //R848:R33[3:2] 
+         priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] & 0xF3) | 0x08;   //R25[3:2]=2'b10; min_lp
+	else
+        priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] & 0xF3) | 0x00;   //R25[3:2]=2'b00; min
+
+	R848_I2C.RegAddr = 0x21;
+	R848_I2C.Data = priv->cfg->R848_Array[25];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+	
+	//Must do MUX before PLL() 
+	if(R848_MUX(priv,RingFreq - R848_IMR_IF, RingFreq, R848_STD_SIZE) != RT_Success)      //IMR MUX (LO, RF)
+		return RT_Fail;
+
+	if(R848_PLL(priv,(RingFreq - R848_IMR_IF), R848_STD_SIZE) != RT_Success)  //IMR PLL
+	    return RT_Fail;
+
+	//Set TF, place after R848_MUX( )
+	//TF is dependent to LNA/Mixer Gain setting
+	if(R848_SetTF(priv,RingFreq, (u8)R848_TF_BEAD) != RT_Success)
+		return RT_Fail;
+
+	//clear IQ_cap
+	IMR_POINT.Iqcap = priv->cfg->R848_Array[3] & 0xFC; // R848:R11[1:0] 
+
+	if(IM_Flag == 0)
+	{
+	     if(R848_IQ(priv,&IMR_POINT) != RT_Success)
+		    return RT_Fail;
+	}
+	else
+	{
+		IMR_POINT.Gain_X = R848_IMR_Data[3].Gain_X;
+		IMR_POINT.Phase_Y = R848_IMR_Data[3].Phase_Y;
+		IMR_POINT.Value = R848_IMR_Data[3].Value;
+		//IMR_POINT.Iqcap = R848_IMR_Data[3].Iqcap;
+		if(R848_F_IMR(priv,&IMR_POINT) != RT_Success)
+			return RT_Fail;
+	}
+
+	//Save IMR Value
+	switch(IMR_MEM)
+	{
+	case 0:
+		R848_IMR_Data[0].Gain_X  = IMR_POINT.Gain_X;
+		R848_IMR_Data[0].Phase_Y = IMR_POINT.Phase_Y;
+		R848_IMR_Data[0].Value = IMR_POINT.Value;
+		R848_IMR_Data[0].Iqcap = IMR_POINT.Iqcap;		
+		break;
+	case 1:
+		R848_IMR_Data[1].Gain_X  = IMR_POINT.Gain_X;
+		R848_IMR_Data[1].Phase_Y = IMR_POINT.Phase_Y;
+		R848_IMR_Data[1].Value = IMR_POINT.Value;
+		R848_IMR_Data[1].Iqcap = IMR_POINT.Iqcap;
+		break;
+	case 2:
+		R848_IMR_Data[2].Gain_X  = IMR_POINT.Gain_X;
+		R848_IMR_Data[2].Phase_Y = IMR_POINT.Phase_Y;
+		R848_IMR_Data[2].Value = IMR_POINT.Value;
+		R848_IMR_Data[2].Iqcap = IMR_POINT.Iqcap;
+		break;
+	case 3:
+		R848_IMR_Data[3].Gain_X  = IMR_POINT.Gain_X;
+		R848_IMR_Data[3].Phase_Y = IMR_POINT.Phase_Y;
+		R848_IMR_Data[3].Value = IMR_POINT.Value;
+		R848_IMR_Data[3].Iqcap = IMR_POINT.Iqcap;
+		break;
+	case 4:
+		R848_IMR_Data[4].Gain_X  = IMR_POINT.Gain_X;
+		R848_IMR_Data[4].Phase_Y = IMR_POINT.Phase_Y;
+		R848_IMR_Data[4].Value = IMR_POINT.Value;
+		R848_IMR_Data[4].Iqcap = IMR_POINT.Iqcap;
+		break;
+    default:
+		R848_IMR_Data[4].Gain_X  = IMR_POINT.Gain_X;
+		R848_IMR_Data[4].Phase_Y = IMR_POINT.Phase_Y;
+		R848_IMR_Data[4].Value = IMR_POINT.Value;
+		R848_IMR_Data[4].Iqcap = IMR_POINT.Iqcap;
+		break;
+	}
+	return RT_Success;
+}
+
+
+
+
+R848_ErrCode R848_GPO( struct r848_priv *priv,R848_GPO_Type R848_GPO_Conrl)
+{
+	I2C_TYPE  R848_I2C;
+
+	if(R848_GPO_Conrl == HI_SIG)	//  R23[0]  
+		priv->cfg->R848_Array[15] |= 0x01;   //high
+	else
+		priv->cfg->R848_Array[15] &= 0xFE;  //low
+	R848_I2C.RegAddr = 0x17;
+	R848_I2C.Data = priv->cfg->R848_Array[15];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	return RT_Success;
+}
+R848_ErrCode R848_InitReg( struct r848_priv *priv,R848_Standard_Type R848_Standard)
+{
+	u8 InitArrayCunt = 0;
+	//I2C_LEN_TYPE R848_I2C_Len;
+	//Write Full Table, Set Xtal Power = highest at initial
+	//R848_I2C_Len.RegAddr = 0x08;   //  R848:0x08
+	//R848_I2C_Len.Len = R848_REG_NUM;
+
+	u8 buf[R848_REG_NUM + 1];
+
+	if(R848_Standard!=R848_DVB_S)
+	{
+		for(InitArrayCunt = 0; InitArrayCunt<R848_REG_NUM; InitArrayCunt ++) {
+			//R848_I2C_Len.Data[InitArrayCunt] = R848_iniArray_hybrid[InitArrayCunt];
+			buf[InitArrayCunt + 1] = R848_iniArray_hybrid[InitArrayCunt];
+			priv->cfg->R848_Array[InitArrayCunt] = R848_iniArray_hybrid[InitArrayCunt];
+		}
+	} else {
+		for (InitArrayCunt = 0; InitArrayCunt<R848_REG_NUM; InitArrayCunt ++) {
+			//R848_I2C_Len.Data[InitArrayCunt] = R848_iniArray_dvbs[InitArrayCunt];
+			buf[InitArrayCunt + 1] = R848_iniArray_dvbs[InitArrayCunt];
+			priv->cfg->R848_Array[InitArrayCunt] = R848_iniArray_dvbs[InitArrayCunt];
+		}
+	}
+//	if(I2C_Write_Len(priv,&R848_I2C_Len) != RT_Success)
+//		return RT_Fail;
+	buf[0] = 0x08;
+	r848_wrm(priv, buf, R848_REG_NUM+1);
+
+	return RT_Success;
+}
+
+
+u8  R848_Filt_Cal_ADC( struct r848_priv *priv,u32 IF_Freq, u8 R848_BW, u8 FilCal_Gap)
+{
+	 u8     u1FilterCodeResult = 0;
+	 u8     u1FilterCode = 0;
+	 u32   u4RingFreq = 72000;
+	 u8     u1FilterCalValue = 0;
+	 u8     u1FilterCalValuePre = 0;
+	 u8     initial_cnt = 0;
+	 u8     i = 0;
+	 I2C_TYPE  R848_I2C;
+	 u8 	R848_Bandwidth = 0x00;
+	 u8   VGA_Count = 0;
+	 u8   VGA_Read = 0;
+
+	 R848_Standard_Type	R848_Standard;
+	 R848_Standard=R848_ATSC; //no set R848_DVB_S
+
+	 //Write initial reg before doing calibration 
+	 if(R848_InitReg(priv,R848_Standard) != RT_Success)        
+		return RT_Fail;
+
+	 if(R848_Cal_Prepare(priv,R848_LPF_CAL) != RT_Success)      
+	      return RT_Fail;
+
+
+
+	 R848_I2C.RegAddr = 0x27;	//  R848:R39[5:2]  
+	 priv->cfg->R848_Array[31] = (priv->cfg->R848_Array[31] & 0xC3) | 0x2C;  
+	 R848_I2C.Data = priv->cfg->R848_Array[31];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	 R848_I2C.RegAddr = 0x12;	//R848:R18[4]  
+	 priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xEF) | 0x00; 
+	 R848_I2C.Data = priv->cfg->R848_Array[10];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	 R848_I2C.RegAddr = 0x25;	//  R848:R37[7]  
+	 priv->cfg->R848_Array[29] = (priv->cfg->R848_Array[29] & 0x7F) | 0x00; 
+	 R848_I2C.Data = priv->cfg->R848_Array[29];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	
+	 R848_I2C.RegAddr = 0x27;	//  R848:R39[7:6]  
+	 priv->cfg->R848_Array[31] = (priv->cfg->R848_Array[31] & 0x3F) | 0x80;  
+	 R848_I2C.Data = priv->cfg->R848_Array[31];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+	
+	 R848_I2C.RegAddr = 0x21;	//  R848:R33[7:0]  
+	 priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] & 0x00) | 0x8B;   //out div=8, RF poly=low band, power=min_lp
+	 R848_I2C.Data = priv->cfg->R848_Array[25];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;	
+
+     //Must do before PLL() 
+	 if(R848_MUX(priv,u4RingFreq + IF_Freq, u4RingFreq, R848_STD_SIZE) != RT_Success)     //FilCal MUX (LO_Freq, RF_Freq)
+	     return RT_Fail;
+
+	 //Set PLL
+	 if(R848_PLL(priv,(u4RingFreq + IF_Freq), R848_STD_SIZE) != RT_Success)   //FilCal PLL
+	       return RT_Fail;
+
+	 //-----below must set after R848_MUX()-------//
+	 //Set LNA TF for RF=72MHz. no use
+
+	 {
+	    R848_I2C.RegAddr = 0x08;	//  R848:R8[6:0]  
+        priv->cfg->R848_Array[0] = (priv->cfg->R848_Array[0] & 0x80) | 0x00;  
+	 }
+     R848_I2C.Data = priv->cfg->R848_Array[0];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+
+	 //Adc=on set 0;
+	 R848_I2C.RegAddr = 0x0F;		//  R848:R15[7]  
+     priv->cfg->R848_Array[7] = (priv->cfg->R848_Array[7] & 0x7F);
+     R848_I2C.Data = priv->cfg->R848_Array[7];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+
+
+	//pwd_vga  vga power on set 0;
+	 R848_I2C.RegAddr = 0x12;	//  R848:R18[7] 
+     priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0x7F);  
+     R848_I2C.Data = priv->cfg->R848_Array[10];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+
+
+
+	 //vga6db normal set 0;
+	 R848_I2C.RegAddr = 0x0B;		// R848:R11[3]  
+     priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xF7);
+     R848_I2C.Data = priv->cfg->R848_Array[3];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+ 	 //Vga Gain = -12dB 
+	 R848_I2C.RegAddr = 0x14;		//  R848:R20[3:0]  
+     priv->cfg->R848_Array[12] = (priv->cfg->R848_Array[12] & 0xF0);
+     R848_I2C.Data = priv->cfg->R848_Array[12];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	
+	 // vcomp = 0
+	 R848_I2C.RegAddr = 0x26;	//  R848:R38[6:5]  
+	 priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0x9F);	
+	 R848_I2C.Data = priv->cfg->R848_Array[30];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+	
+	 //Set BW=8M, HPF corner narrowest; 1.7M disable
+     R848_I2C.RegAddr = 0x13;	//  R848:R19[7:0]  
+	 priv->cfg->R848_Array[11] = (priv->cfg->R848_Array[11] & 0x00);	  
+     R848_I2C.Data = priv->cfg->R848_Array[11];		
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;	
+
+	 //------- increase VGA power to let ADC read value significant ---------//
+
+	 R848_I2C.RegAddr = 0x12;	//  R848:R18[3:0]  
+     priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xF0) | 0;  //filter code=0
+     R848_I2C.Data = priv->cfg->R848_Array[10];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+
+	 for(VGA_Count=0; VGA_Count < 16; VGA_Count ++)
+	 {
+		R848_I2C.RegAddr = 0x14;	//  R848:R20[3:0]  
+		R848_I2C.Data    = (priv->cfg->R848_Array[12] & 0xF0) + VGA_Count;  
+		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+			return RT_Fail;
+
+		msleep(10); //
+		
+		if(R848_Muti_Read(priv,&VGA_Read) != RT_Success)
+			return RT_Fail;
+
+		if(VGA_Read > 40)
+			break;
+	 }
+
+	 //------- Try suitable BW --------//
+
+	 if(R848_BW==0x60) //6M
+         initial_cnt = 1;  //try 7M first
+	 else
+		 initial_cnt = 0;  //try 8M first
+
+	 for(i=initial_cnt; i<3; i++)
+	 {
+         if(i==0)
+             R848_Bandwidth = 0x00; //8M
+		 else if(i==1)
+			 R848_Bandwidth = 0x40; //7M
+		 else
+			 R848_Bandwidth = 0x60; //6M
+
+		 R848_I2C.RegAddr = 0x13;	//  R848:R19[7:0]  
+	     priv->cfg->R848_Array[11] = (priv->cfg->R848_Array[11] & 0x00) | R848_Bandwidth;	  
+         R848_I2C.Data = priv->cfg->R848_Array[11];		
+         if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		      return RT_Fail;	
+
+		 // read code 0
+		 R848_I2C.RegAddr = 0x12;	//  R848:R18[3:0]  
+		 priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xF0) | 0;  //code 0
+		 R848_I2C.Data = priv->cfg->R848_Array[10];
+		 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+			  return RT_Fail;
+
+		 msleep(10); //delay ms
+	     
+		 if(R848_Muti_Read(priv,&u1FilterCalValuePre) != RT_Success)
+			  return RT_Fail;
+
+		 //read code 13
+		 R848_I2C.RegAddr = 0x12;	// R848:R18[3:0]  
+		 priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xF0) | 13;  //code 13
+		 R848_I2C.Data = priv->cfg->R848_Array[10];
+		 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+			  return RT_Fail;
+
+		 msleep(10); //delay ms
+	     
+		 if(R848_Muti_Read(priv,&u1FilterCalValue) != RT_Success)
+			  return RT_Fail;
+
+		 if(u1FilterCalValuePre > (u1FilterCalValue+8))  //suitable BW found
+			 break;
+	 }
+
+     //-------- Try LPF filter code ---------//
+	 u1FilterCalValuePre = 0;
+	 for(u1FilterCode=0; u1FilterCode<16; u1FilterCode++)
+	 {
+         R848_I2C.RegAddr = 0x12;	//  R848:R18[3:0]  
+         priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xF0) | u1FilterCode;
+         R848_I2C.Data = priv->cfg->R848_Array[10];
+         if(I2C_Write(priv,&R848_I2C) != RT_Success)
+              return RT_Fail;
+
+		 msleep(10); //delay ms
+
+		 if(R848_Muti_Read(priv,&u1FilterCalValue) != RT_Success)
+		      return RT_Fail;
+
+		 if(u1FilterCode==0)
+              u1FilterCalValuePre = u1FilterCalValue;
+
+		 if((u1FilterCalValue+FilCal_Gap) < u1FilterCalValuePre)
+		 {
+			 u1FilterCodeResult = u1FilterCode;
+			  break;
+		 }
+
+	 }
+
+	 if(u1FilterCode==16)
+          u1FilterCodeResult = 15;
+
+	  return u1FilterCodeResult;
+
+}
+
+
+R848_ErrCode R848_DVBS_Setting( struct r848_priv *priv,R848_Set_Info R848_INFO)
+{
+	 u32	LO_KHz;
+	 u8 fine_tune,Coarse_tune;
+	// u8 test_coar=0x0D;
+	 u32 Coarse;
+	I2C_TYPE  R848_I2C;
+
+//	if(R848_INFO.R848_Standard != R848_pre_standard)
+	{
+		 if(R848_InitReg(priv,R848_INFO.R848_Standard) != RT_Success)      
+		     return RT_Fail;
+	}
+    priv->cfg->R848_pre_standard = R848_INFO.R848_Standard;
+
+
+	 LO_KHz = R848_INFO.RF_KHz;
+
+	if(R848_PLL(priv,LO_KHz, R848_INFO.R848_Standard)!= RT_Success)
+	{
+		return RT_Fail;
+	}
+	
+	//VTH/VTL
+	if((R848_INFO.RF_KHz >= 1200000)&&(R848_INFO.RF_KHz <= 1750000))
+	{
+		priv->cfg->R848_Array[23]=(priv->cfg->R848_Array[23] & 0x00) | 0x93;			//R848:R31[7:0]    1.24/0.64
+	}
+	else
+	{	
+		priv->cfg->R848_Array[23]=(priv->cfg->R848_Array[23] & 0x00) | 0x83;			//R848:R31[7:0]   1.14/0.64
+	}
+	R848_I2C.RegAddr = 0x1F;
+	R848_I2C.Data = priv->cfg->R848_Array[23];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+
+
+	if(R848_INFO.RF_KHz >= 2000000) 
+	{
+		R848_I2C.RegAddr = 0x2E;
+		priv->cfg->R848_Array[38]=(priv->cfg->R848_Array[38] & 0xCF) | 0x20;			//R848:R46[4:5]
+		R848_I2C.Data = priv->cfg->R848_Array[38];
+		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+	}
+
+
+	if((R848_INFO.RF_KHz >= 1600000) && (R848_INFO.RF_KHz <= 1950000))
+	{
+		priv->cfg->R848_Array[35] |= 0x20; //LNA Mode with att   //R710 R2[6]    R848:R43[5]   43-8=35   43(0x2B) is addr ; [35] is data
+		//priv->cfg->R848_Array[36] |= 0x04; //Mixer Buf -3dB		  //R710 R8[7]    R848:R44[2]   44-8=36   44(0x2C) is addr ; [36] is data
+	}
+	else
+	{
+		priv->cfg->R848_Array[35] &= 0xDF; //LNA Mode no att
+		//priv->cfg->R848_Array[36] &= 0xFB; //Mixer Buf off
+	}
+
+	R848_I2C.RegAddr = 0x2B;
+	R848_I2C.Data = priv->cfg->R848_Array[35];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	return RT_Fail;
+
+
+	R848_I2C.RegAddr = 0x2C;
+	R848_I2C.Data = priv->cfg->R848_Array[36];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	return RT_Fail;
+
+
+	//Output Signal Mode    (  O is diff  ; 1 is single  )
+	if(R848_INFO.R848_DVBS_OutputSignal_Mode != SINGLEOUT)
+	{
+		priv->cfg->R848_Array[35] &=0x7F;
+	}
+	else
+	{
+		priv->cfg->R848_Array[35] |=0x80;  //R710 R11[4]    R848:R43[7]   43-8=35   43(0x2B) is addr ; [35] is data
+	}
+
+	R848_I2C.RegAddr = 0x2B;
+	R848_I2C.Data = priv->cfg->R848_Array[35];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	return RT_Fail;
+
+
+
+	//AGC Type  //R13[4] Negative=0 ; Positive=1;
+	if(R848_INFO.R848_DVBS_AGC_Mode != AGC_POSITIVE)
+	{
+		priv->cfg->R848_Array[37] &= 0xF7;
+	}
+	else
+	{
+		priv->cfg->R848_Array[37] |= 0x08;  //R710 R13[4]    R848:R45[3]   45-8=37   45(0x2D) is addr ; [37] is data
+	}
+	R848_I2C.RegAddr = 0x2D;
+	R848_I2C.Data = priv->cfg->R848_Array[37];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	return RT_Fail;
+
+
+
+	if (R848_INFO.DVBS_BW >67400)
+	{
+		fine_tune=1;
+		Coarse =(( R848_INFO.DVBS_BW -67400) /1600)+31;
+		if((( R848_INFO.DVBS_BW -67400) % 1600) > 0)
+		Coarse+=1;
+	}
+
+	else if((R848_INFO.DVBS_BW >62360)&&(R848_INFO.DVBS_BW<=67400))
+	{
+		Coarse=31;
+		fine_tune=1;		
+	}
+	else if((R848_INFO.DVBS_BW >38000)&&(R848_INFO.DVBS_BW<=62360))
+	{
+		fine_tune=1;	
+		Coarse =(( R848_INFO.DVBS_BW -38000) /1740)+16;
+		if((( R848_INFO.DVBS_BW -38000) % 1740) > 0)
+		Coarse+=1;
+				
+	}
+	else if(R848_INFO.DVBS_BW<=5000)
+	{	
+		Coarse=0;
+		fine_tune=0;
+	}
+	else if((R848_INFO.DVBS_BW>5000) && (R848_INFO.DVBS_BW<=8000))
+	{
+		Coarse=0;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>8000) && (R848_INFO.DVBS_BW<=10000))
+	{
+		Coarse=1;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>10000) && (R848_INFO.DVBS_BW<=12000))
+	{
+		Coarse=2;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>12000) && (R848_INFO.DVBS_BW<=14200))
+	{
+		Coarse=3;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>14200) && (R848_INFO.DVBS_BW<=16000))
+	{
+		Coarse=4;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>16000) && (R848_INFO.DVBS_BW<=17800))
+	{
+		Coarse=5;
+		fine_tune=0;
+	}
+	else if((R848_INFO.DVBS_BW>17800) && (R848_INFO.DVBS_BW<=18600))
+	{
+		Coarse=5;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>18600) && (R848_INFO.DVBS_BW<=20200))
+	{
+		Coarse=6;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>20200) && (R848_INFO.DVBS_BW<=22400))
+	{
+		Coarse=7;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>22400) && (R848_INFO.DVBS_BW<=24600))
+	{
+		Coarse=9;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>24600) && (R848_INFO.DVBS_BW<=25400))
+	{
+		Coarse=10;
+		fine_tune=0;
+	}
+	else if((R848_INFO.DVBS_BW>25400) && (R848_INFO.DVBS_BW<=26000))
+	{
+		Coarse=10;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>26000) && (R848_INFO.DVBS_BW<=27200))
+	{
+		Coarse=11;
+		fine_tune=0;
+	}
+	else if((R848_INFO.DVBS_BW>27200) && (R848_INFO.DVBS_BW<=27800))
+	{
+		Coarse=11;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>27800) && (R848_INFO.DVBS_BW<=30200))
+	{
+		Coarse=12;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>30200) && (R848_INFO.DVBS_BW<=32600))
+	{
+		Coarse=13;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>32600) && (R848_INFO.DVBS_BW<=33800))
+	{
+		Coarse=14;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>33800) && (R848_INFO.DVBS_BW<=36800))
+	{
+		Coarse=15;
+		fine_tune=1;
+	}
+	else if((R848_INFO.DVBS_BW>36800) && (R848_INFO.DVBS_BW<=38000))
+	{
+		Coarse=16;
+		fine_tune=1;
+	}
+
+	Coarse_tune = (unsigned char) Coarse;//coras filter value
+
+	//fine tune and coras filter write		
+	R848_I2C.RegAddr = 0x2F;
+	priv->cfg->R848_Array[39] &= 0x00;		//47-8=39
+	priv->cfg->R848_Array[39] = ((priv->cfg->R848_Array[39] | ( fine_tune<< 6 ) ) | ( Coarse_tune));
+	R848_I2C.Data = priv->cfg->R848_Array[39];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	//Set GPO Low
+	R848_I2C.RegAddr = 0x17;	// R848:R23[4:2]  23-8=15  23(0x17) is addr ; [15] is data
+	priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0xFE);
+	R848_I2C.Data = priv->cfg->R848_Array[15];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	return RT_Fail;
+
+
+	return RT_Success;
+}
+
+
+
+
+R848_Sys_Info_Type R848_Sys_Sel( struct r848_priv *priv,R848_Standard_Type R848_Standard)
+	{
+	
+		R848_Sys_Info_Type R848_Sys_Info;
+	
+		switch (R848_Standard)
+		{
+		case R848_DVB_T_6M: 
+		case R848_DVB_T2_6M: 
+			R848_Sys_Info.IF_KHz=4570;					  //IF
+			R848_Sys_Info.BW=0x40;							//BW=7M    R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7450; 		 //CAL IF
+			R848_Sys_Info.HPF_COR=0x05; 			 //R19[3:0]=5
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+	
+	
+		case R848_DVB_T_7M:  
+		case R848_DVB_T2_7M:  
+			R848_Sys_Info.IF_KHz=4570;					   //IF
+			R848_Sys_Info.BW=0x40;							 //BW=7M	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7750; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x08; 			 //R19[3:0]=8  (1.45M)
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+		case R848_DVB_T_8M: 
+		case R848_DVB_T2_8M: 
+			R848_Sys_Info.IF_KHz=4570;					   //IF
+			R848_Sys_Info.BW=0x00;							 //BW=8M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8130; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x09; 			 //R19[3:0]=9
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+		case R848_DVB_T2_1_7M: 
+			R848_Sys_Info.IF_KHz=1900;
+			R848_Sys_Info.BW=0x40;							 //BW=7M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7800; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x08; 			 //R19[3:0]=8
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_DVB_T2_10M: 
+			R848_Sys_Info.IF_KHz=5600;
+			R848_Sys_Info.BW=0x00;							 //BW=8M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=10800;		 //CAL IF
+			R848_Sys_Info.HPF_COR=0x0C; 			 //R19[3:0]=12
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_DVB_C_8M:  
+#if (FOR_TDA10024==1)
+			R848_Sys_Info.IF_KHz=5070;
+			R848_Sys_Info.BW=0x00;							 //BW=8M   R11[6:5]
+			R848_Sys_Info.FILT_CAL_IF=9200; 		  //CAL IF //8750
+			R848_Sys_Info.HPF_COR=0x0A; 			 //R19[3:0]=10
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=1, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x02;	 //R38[1:0]=10, lna=max-1 & Buf 4
+#else
+			R848_Sys_Info.IF_KHz=5070;
+			R848_Sys_Info.BW=0x00;							 //BW=8M   R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=9000; 		  //CAL IF //9150
+			R848_Sys_Info.HPF_COR=0x0A; 			 //R19[3:0]=10
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x02;	 //R38[1:0]=10, lna=max-1 & Buf 4
+#endif
+			break;
+	
+		case R848_DVB_C_6M:  
+			R848_Sys_Info.IF_KHz=5070;
+			R848_Sys_Info.BW=0x40;							//BW=7M   R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8025; 		 //CAL IF	
+			R848_Sys_Info.HPF_COR=0x03; 			 //R19[3:0]=3 //3
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_J83B:  
+			R848_Sys_Info.IF_KHz=5070;
+			R848_Sys_Info.BW=0x40;							//BW=7M   R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8025; 		 //CAL IF  
+			R848_Sys_Info.HPF_COR=0x03; 			 //R19[3:0]=3 //3
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_ISDB_T: 
+			R848_Sys_Info.IF_KHz=4063;
+			R848_Sys_Info.BW=0x40;							//BW=7M 	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7000; 		 //CAL IF  //7200
+			R848_Sys_Info.HPF_COR=0x08; 			 //R19[3:0]=8
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+		case R848_ISDB_T_4570:
+			R848_Sys_Info.IF_KHz=4570;					  //IF
+			R848_Sys_Info.BW=0x40;							//BW=7M
+			R848_Sys_Info.FILT_CAL_IF=7250; 		 //CAL IF
+			R848_Sys_Info.HPF_COR=0x05; 			 //R19[3:0]=5 (2.0M)
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8, hpf+3
+			break;
+	
+		case R848_DTMB_4570: 
+			R848_Sys_Info.IF_KHz=4570;
+			R848_Sys_Info.BW=0x00;							 //BW=8M   R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8330; 		  //CAL IF	//8130
+			R848_Sys_Info.HPF_COR=0x0B; 			 //R19[3:0]=11
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_DTMB_6000: 
+			R848_Sys_Info.IF_KHz=6000;
+			R848_Sys_Info.BW=0x00;							 //BW=8M	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=9550; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x03; 			 //R19[3:0]=3
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x02;	 //R38[1:0]=10, lna=max-1 & Buf 4
+			break;
+	
+		case R848_DTMB_6M_BW_IF_5M:
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x40;							 //BW=7M
+			R848_Sys_Info.FILT_CAL_IF=7700; 		  //CAL IF	
+			R848_Sys_Info.HPF_COR=0x04; 			 //R19[3:0]=4
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1 & Buf 4, hpf+1
+			break;
+	
+		case R848_DTMB_6M_BW_IF_4500:
+			R848_Sys_Info.IF_KHz=4500;
+			R848_Sys_Info.BW=0x40;							 //BW=7M
+			R848_Sys_Info.FILT_CAL_IF=7000; 		  //CAL IF	
+			R848_Sys_Info.HPF_COR=0x05; 			 //R19[3:0]=5
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x02;	 //R38[1:0]=10, lna=max-1 & Buf 4, hpf+3
+			break;
+		
+		case R848_ATSC:  
+			R848_Sys_Info.IF_KHz=5070;
+			R848_Sys_Info.BW=0x40;							//BW=7M 	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7900; 		 //CAL IF	  20130621 Ryan Modify
+			R848_Sys_Info.HPF_COR=0x04; 			 //R19[3:0]=4 
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_DVB_T_6M_IF_5M: 
+		case R848_DVB_T2_6M_IF_5M: 
+			R848_Sys_Info.IF_KHz=5000;					  //IF
+			R848_Sys_Info.BW=0x40;							//BW=7M 	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7800; 		 //CAL IF
+			R848_Sys_Info.HPF_COR=0x04; 			 //R19[3:0]=4
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+		case R848_DVB_T_7M_IF_5M:  
+		case R848_DVB_T2_7M_IF_5M:	
+			R848_Sys_Info.IF_KHz=5000;					   //IF
+			R848_Sys_Info.BW=0x00;							 //BW=8M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8300; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x07; 			 //R19[3:0]=7
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+		case R848_DVB_T_8M_IF_5M: 
+		case R848_DVB_T2_8M_IF_5M: 
+			R848_Sys_Info.IF_KHz=5000;					   //IF
+			R848_Sys_Info.BW=0x00;							 //BW=8M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8500; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x08; 			 //R19[3:0]=8
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+		case R848_DVB_T2_1_7M_IF_5M: 
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x60;							 //BW=6M	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=5900; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x01; 			 //R19[3:0]=1
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_DVB_C_8M_IF_5M:  
+	//	case R848_DVB_C_CHINA_IF_5M:   //RF>115MHz
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x00;							 //BW=8M	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=9000; 		  //CAL IF 
+			R848_Sys_Info.HPF_COR=0x0A; 			 //R19[3:0]=10
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x02;	 //R38[1:0]=10, lna=max-1 & Buf 4
+			break;
+	
+		case R848_DVB_C_6M_IF_5M:  
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x40;							//BW=7M 	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8100; 		 //CAL IF	
+			R848_Sys_Info.HPF_COR=0x04; 			 //R19[3:0]=4 
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_J83B_IF_5M:  
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x40;							//BW=7M    R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8025; 		 //CAL IF  
+			R848_Sys_Info.HPF_COR=0x03; 			 //R19[3:0]=3 
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_ISDB_T_IF_5M:
+			R848_Sys_Info.IF_KHz=5000;	
+			R848_Sys_Info.BW=0x40;							//BW=7M 	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7940; 		 //CAL IF  
+			R848_Sys_Info.HPF_COR=0x04; 			 //R19[3:0]=4
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x03;	 //R38[1:0]=11, buf 8
+			break;
+	
+		case R848_DTMB_IF_5M: 
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x00;							 //BW=8M	  R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8650; 		  //CAL IF	
+			R848_Sys_Info.HPF_COR=0x09; 			 //R19[3:0]=9
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x02;	 //R38[1:0]=0, lna=max-1
+			break;
+		
+		case R848_ATSC_IF_5M:  
+			R848_Sys_Info.IF_KHz=5000;
+			R848_Sys_Info.BW=0x40;							//BW=7M 	 R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7900; 		 //CAL IF	
+			R848_Sys_Info.HPF_COR=0x04; 			 //R19[3:0]=4 
+			R848_Sys_Info.FILT_EXT_ENA=0x00;	  //R19[4]=0, ext disable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		case R848_FM:  
+			R848_Sys_Info.IF_KHz=2400;
+			R848_Sys_Info.BW=0x40;							 //BW=7M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=7200; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x02; 			 //R19[3:0]=2
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		default:  //R848_DVB_T_8M
+			R848_Sys_Info.IF_KHz=4570;					   //IF
+			R848_Sys_Info.BW=0x00;							 //BW=8M	R848:R19[6:5]
+			R848_Sys_Info.FILT_CAL_IF=8330; 		  //CAL IF
+			R848_Sys_Info.HPF_COR=0x0B; 			 //R19[3:0]=11
+			R848_Sys_Info.FILT_EXT_ENA=0x10;	  //R19[4]=1, ext enable
+			R848_Sys_Info.FILT_EXT_WIDEST=0x00;//R38[2]=0, ext normal
+			R848_Sys_Info.FILT_EXT_POINT=0x00;	 //R38[1:0]=0, lna=max-1
+			break;
+	
+		}
+	
+		//R848_Sys_Info.INDUC_BIAS = 0x01;	   //normal 	 
+		//R848_Sys_Info.SWCAP_CLK = 0x01;	  //32k 	  
+		R848_Sys_Info.SWCAP_CLK = 0x02; 	 //8k		 //AGC 500Hz map to 8k	R26[1:0]
+		R848_Sys_Info.NA_PWR_DET = 0x00;   //on 								R38[7]
+			
+		R848_Sys_Info.TF_CUR = 0x40;				  //low  R11[6]=1
+		R848_Sys_Info.SWBUF_CUR = 0x04; 		 //low	R12[2]=1
+	
+	
+	
+	/*	switch(R848_Standard)
+		{
+			case R848_DVB_T2_6M: 
+			case R848_DVB_T2_7M:
+			case R848_DVB_T2_8M:
+			case R848_DVB_T2_1_7M: 
+			case R848_DVB_T2_10M: 
+			case R848_DVB_T2_6M_IF_5M:
+			case R848_DVB_T2_7M_IF_5M:
+			case R848_DVB_T2_8M_IF_5M:
+			case R848_DVB_T2_1_7M_IF_5M: 
+				R848_Sys_Info.AGC_CLK = 0x1C;			   //250Hz	 R26[4:2] 
+			break;
+			default: 
+				R848_Sys_Info.AGC_CLK = 0x00;			   //1k   R26[4:2] 
+			break;
+		}*/
+	
+		//Filter 3dB
+		switch(R848_Standard)
+		{
+			case R848_DVB_C_8M_IF_5M:
+				R848_Sys_Info.FILT_3DB = 0x08;		   // ON	  R38[3]
+			break;
+			default: 
+				R848_Sys_Info.FILT_3DB = 0x00;		   // OFF	  R38[3]
+			break;
+		}
+	
+		R848_Sys_Info.FILT_COMP = 0x20; 
+		R848_Sys_Info.FILT_CUR = 0x00;		 //highest R18[6:5]
+	
+	
+		//BW 1.7M
+		if((R848_Standard==R848_DVB_T2_1_7M) || (R848_Standard==R848_FM))
+			R848_Sys_Info.V17M = 0x80;		 //enable,	R19[7]
+		else
+			R848_Sys_Info.V17M = 0x00;		 //disable, (include DVBT2 1.7M IF=5MHz) R19[7]
+	
+		//TF Type select
+		switch(R848_Standard)
+		{
+			case R848_DTMB_4570:
+			case R848_DTMB_6000:
+			case R848_DTMB_6M_BW_IF_5M:
+			case R848_DTMB_6M_BW_IF_4500:
+			case R848_DTMB_IF_5M:
+					if(priv->cfg->R848_DetectTfType == R848_UL_USING_BEAD )
+					{
+						priv->cfg->R848_SetTfType = R848_TF_82N_BEAD;	 
+					}
+					else
+					{
+						priv->cfg->R848_SetTfType = R848_TF_82N_270N;	 
+					}
+				 break; 
+	
+			default:		
+					if(priv->cfg->R848_DetectTfType == R848_UL_USING_BEAD)
+					{
+						priv->cfg->R848_SetTfType = R848_TF_82N_BEAD;	 
+					}
+					else
+					{
+						priv->cfg->R848_SetTfType = R848_TF_82N_270N;	 
+					}	
+				break;
+		}
+	
+		return R848_Sys_Info;
+	}
+
+
+
+R848_SysFreq_Info_Type R848_SysFreq_Sel(struct r848_priv *priv,R848_Standard_Type R848_Standard,u32 RF_freq)
+{
+	R848_SysFreq_Info_Type R848_SysFreq_Info;
+	switch(R848_Standard) {
+	case R848_DVB_T_6M:
+	case R848_DVB_T_7M:
+	case R848_DVB_T_8M:
+	case R848_DVB_T_6M_IF_5M:
+	case R848_DVB_T_7M_IF_5M:
+	case R848_DVB_T_8M_IF_5M:
+	case R848_DVB_T2_6M:
+	case R848_DVB_T2_7M:
+	case R848_DVB_T2_8M:
+	case R848_DVB_T2_1_7M:
+	case R848_DVB_T2_10M:
+	case R848_DVB_T2_6M_IF_5M:
+	case R848_DVB_T2_7M_IF_5M:
+	case R848_DVB_T2_8M_IF_5M:
+	case R848_DVB_T2_1_7M_IF_5M:
+		if((RF_freq>=300000)&&(RF_freq<=472000))
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA4;	   // LNA VTH/L=1.34/0.74     (R31=0xA4)
+			R848_SysFreq_Info.MIXER_TOP=0x05;	       // MIXER TOP=10        (R36[3:0]=4'b0101)
+			R848_SysFreq_Info.MIXER_VTH_L=0x95;   // MIXER VTH/L=1.24/0.84  (R32=0x95)
+			R848_SysFreq_Info.NRB_TOP=0xC0;            // Nrb TOP=3                       (R36[7:4]=4'b1100)
+
+		}
+		else if((RF_freq>=184000) && (RF_freq<=299000))
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA5;	   // LNA VTH/L=1.34/0.84     (R31=0xA5)
+			R848_SysFreq_Info.MIXER_TOP=0x04;	       // MIXER TOP=11        (R36[3:0]=4'b0101)
+			R848_SysFreq_Info.MIXER_VTH_L=0xA6;   // MIXER VTH/L=1.34/0.94  (R32=0xA6)
+			R848_SysFreq_Info.NRB_TOP=0x70;            // Nrb TOP=8                       (R36[7:4]=4'b1100)
+		}
+		else
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA5;	   // LNA VTH/L=1.34/0.84     (R31=0xA5)
+			R848_SysFreq_Info.MIXER_TOP=0x05;	       // MIXER TOP=10        (R36[3:0]=4'b0101)
+			R848_SysFreq_Info.MIXER_VTH_L=0x95;   // MIXER VTH/L=1.24/0.84  (R32=0x95)
+			R848_SysFreq_Info.NRB_TOP=0xC0;            // Nrb TOP=3                       (R36[7:4]=4'b1100)
+		}
+		    R848_SysFreq_Info.LNA_TOP=0x03;		       // LNA TOP=4           (R35[2:0]=3'b011)
+			R848_SysFreq_Info.RF_TOP=0x40;               // RF TOP=5                        (R34[7:5]=3'b010)                 
+			R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)	
+		break;
+
+	case R848_DVB_C_8M:
+	case R848_DVB_C_6M:
+	case R848_J83B:
+	case R848_DVB_C_8M_IF_5M:
+	case R848_DVB_C_6M_IF_5M:
+	case R848_J83B_IF_5M:
+		if(RF_freq<165000)
+		{
+			R848_SysFreq_Info.LNA_TOP=0x02;		       // LNA TOP=5                    (R35[2:0]=3'b010)
+			R848_SysFreq_Info.LNA_VTH_L=0x94;	   // LNA VTH/L=1.24/0.74     (R31=0x94)
+			R848_SysFreq_Info.RF_TOP=0x80;               // RF TOP=3                        (R34[7:5]=3'b100)
+			R848_SysFreq_Info.NRB_TOP=0x90;            // Nrb TOP=6                       (R36[7:4]=4'b1001)   //R848:R36[7:4]
+		}
+		else if((RF_freq>=165000) && (RF_freq<=299000))
+		{
+			R848_SysFreq_Info.LNA_TOP=0x03;		       // LNA TOP=4                    (R35[2:0]=3'b011)
+			R848_SysFreq_Info.LNA_VTH_L=0x94;	   // LNA VTH/L=1.24/0.74     (R31=0x94)
+			R848_SysFreq_Info.RF_TOP=0x80;               // RF TOP=3                        (R34[7:5]=3'b100)
+			R848_SysFreq_Info.NRB_TOP=0x90;            // Nrb TOP=6                       (R36[7:4]=4'b1001)
+		}
+		else if((RF_freq>299000) && (RF_freq<=345000))
+		{
+			R848_SysFreq_Info.LNA_TOP=0x03;		        // LNA TOP=4                    (R35[2:0]=3'b011)
+			R848_SysFreq_Info.LNA_VTH_L=0xA4;			// LNA VTH/L=1.34/0.74     (R31=0xA4)
+			R848_SysFreq_Info.RF_TOP=0x80;              // RF TOP=3                        (R34[7:5]=3'b100)
+			R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                       (R36[7:4]=4'b1001)
+		}
+		else if((RF_freq>345000) && (RF_freq<=472000))
+		{
+			R848_SysFreq_Info.LNA_TOP=0x04;		        // LNA TOP=3                    (R35[2:0]=3'b100)
+			R848_SysFreq_Info.LNA_VTH_L=0x93;		    // LNA VTH/L=1.24/0.64     (R31=0x93)
+			R848_SysFreq_Info.RF_TOP=0xA0;				// RF TOP=2                        (R34[7:5]=3'b101)
+			R848_SysFreq_Info.NRB_TOP=0x20;             // Nrb TOP=13                       (R36[7:4]=4'b0010)
+		}
+		else
+		{
+			R848_SysFreq_Info.LNA_TOP=0x04;		        // LNA TOP=3                    (R35[2:0]=3'b100)
+			R848_SysFreq_Info.LNA_VTH_L=0x83;		    // LNA VTH/L=1.14/0.64     (R31=0x83)
+			R848_SysFreq_Info.RF_TOP=0xA0;              // RF TOP=2                        (R34[7:5]=3'b101)
+			R848_SysFreq_Info.NRB_TOP=0x20;             // Nrb TOP=13                       (R36[7:4]=4'b0010)
+		}
+			R848_SysFreq_Info.MIXER_TOP=0x05;	        // MIXER TOP=10               (R36[3:0]=4'b0100)
+			R848_SysFreq_Info.MIXER_VTH_L=0x95;			// MIXER VTH/L=1.24/0.84  (R32=0x95)
+		break;
+
+	case R848_ISDB_T:
+	case R848_ISDB_T_4570:
+	case R848_ISDB_T_IF_5M:
+		if((RF_freq>=300000)&&(RF_freq<=472000))
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA4;	   // LNA VTH/L=1.34/0.74     (R31=0xA4)
+		}
+		else
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA5;	   // LNA VTH/L=1.34/0.84     (R31=0xA5)
+		}
+			R848_SysFreq_Info.LNA_TOP=0x03;		       // LNA TOP=4                    (R35[2:0]=3'b011)
+			R848_SysFreq_Info.MIXER_TOP=0x05;	       // MIXER TOP=10               (R36[3:0]=4'b0101)
+			R848_SysFreq_Info.MIXER_VTH_L=0x95;   // MIXER VTH/L=1.24/0.84  (R32=0x95)
+			R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			//R848_SysFreq_Info.NRB_TOP=0x20;            // Nrb TOP=13                       (R36[7:4]=4'b0010)
+			R848_SysFreq_Info.NRB_TOP=0xB0;            // Nrb TOP=4                       (R36[7:4]=4'b1011)
+			R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		break;
+
+	case R848_DTMB_4570:
+	case R848_DTMB_6000:
+	case R848_DTMB_6M_BW_IF_5M:
+	case R848_DTMB_6M_BW_IF_4500:
+	case R848_DTMB_IF_5M:
+		if((RF_freq>=300000)&&(RF_freq<=472000))
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA4;	   // LNA VTH/L=1.34/0.74     (R31=0xA4)
+		}
+		else
+		{
+			R848_SysFreq_Info.LNA_VTH_L=0xA5;	   // LNA VTH/L=1.34/0.84     (R31=0xA5)
+		}
+			R848_SysFreq_Info.LNA_TOP=0x03;		       // LNA TOP=4                    (R35[2:0]=3'b011)
+			R848_SysFreq_Info.MIXER_TOP=0x05;	       // MIXER TOP=10               (R36[3:0]=4'b0100)
+			R848_SysFreq_Info.MIXER_VTH_L=0x95;   // MIXER VTH/L=1.24/0.84  (R32=0x95)
+			R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			R848_SysFreq_Info.NRB_TOP=0xA0;            // Nrb TOP=5                       (R36[7:4]=4'b1010)
+			R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		break;
+
+	case R848_ATSC:
+	case R848_ATSC_IF_5M:
+		if(priv->cfg->R848_DetectTfType==R848_UL_USING_BEAD) {
+		   if(RF_freq<88000)
+		   {
+		       R848_SysFreq_Info.LNA_TOP=0x03;	 	       // LNA TOP=4                    (R35[2:0]=3'b011)
+			   R848_SysFreq_Info.LNA_VTH_L=0xA5;	       // LNA VTH/L=1.34/0.84     (R31=0xA5)
+			   R848_SysFreq_Info.RF_TOP=0xC0;               // RF TOP=1                        (R34[7:5]=3'b110)
+			   R848_SysFreq_Info.NRB_TOP=0x30;             // Nrb TOP=12                    (R36[7:4]=4'b0011)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=88000) && (RF_freq<104000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x02;		       // LNA TOP=5                    (R35[2:0]=3'b010)
+			   R848_SysFreq_Info.LNA_VTH_L=0xA5;	       // LNA VTH/L=1.34/0.84     (R31=0xA5)		
+			   R848_SysFreq_Info.RF_TOP=0xA0;               // RF TOP=2                        (R34[7:5]=3'b101)
+			   R848_SysFreq_Info.NRB_TOP=0x30;             // Nrb TOP=12                    (R36[7:4]=4'b0011)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=104000) && (RF_freq<156000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+			   R848_SysFreq_Info.LNA_VTH_L=0xA5;	       // LNA VTH/L=1.34/0.84     (R31=0xA5)		
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x30;             // Nrb TOP=12                    (R36[7:4]=4'b0011)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=156000) && (RF_freq<464000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+			   R848_SysFreq_Info.LNA_VTH_L=0xA5;	       // LNA VTH/L=1.34/0.84     (R31=0xA5)		
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=464000) && (RF_freq<500000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+			   R848_SysFreq_Info.LNA_VTH_L=0xB6;	       // LNA VTH/L=1.44/0.94     (R31=0xB6)		
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else
+		   {
+				   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+				   R848_SysFreq_Info.LNA_VTH_L=0x94;	       // LNA VTH/L=1.24/0.74     (R31=0x94)		
+				   R848_SysFreq_Info.RF_TOP=0x40;               // RF TOP=5                        (R34[7:5]=3'b010)
+				   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+				   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+	   }
+	   else  //270n
+	   {
+		if(RF_freq<88000)
+		{
+		       R848_SysFreq_Info.LNA_TOP=0x02;	 	       // LNA TOP=5                    (R35[2:0]=3'b010)
+			   R848_SysFreq_Info.LNA_VTH_L=0x94;	       // LNA VTH/L=1.24/0.74     (R31=0x94)
+			   R848_SysFreq_Info.RF_TOP=0x80;               // RF TOP=3                        (R34[7:5]=3'b100)
+			   R848_SysFreq_Info.NRB_TOP=0xC0;             // Nrb TOP=3                    (R36[7:4]=4'b1100)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=88000) && (RF_freq<104000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x02;		       // LNA TOP=5                    (R35[2:0]=3'b010)
+			   R848_SysFreq_Info.LNA_VTH_L=0x94;	       // LNA VTH/L=1.24/0.74     (R31=0x94)
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=104000) && (RF_freq<248000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+			   R848_SysFreq_Info.LNA_VTH_L=0x94;	       // LNA VTH/L=1.24/0.74     (R31=0x94)	
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=248000) && (RF_freq<464000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+			   R848_SysFreq_Info.LNA_VTH_L=0xA5;	       // LNA VTH/L=1.34/0.84     (R31=0xA5)		
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+		   else if((RF_freq>=464000) && (RF_freq<500000))
+		   {
+			   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+			   R848_SysFreq_Info.LNA_VTH_L=0xB6;	       // LNA VTH/L=1.44/0.94     (R31=0xB6)		
+			   R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+			   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+			   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   } else {
+				   R848_SysFreq_Info.LNA_TOP=0x01;		       // LNA TOP=6                    (R35[2:0]=3'b001)
+				   R848_SysFreq_Info.LNA_VTH_L=0x94;	       // LNA VTH/L=1.24/0.74     (R31=0x94)
+				   R848_SysFreq_Info.RF_TOP=0x40;               // RF TOP=5                        (R34[7:5]=3'b010)
+				   R848_SysFreq_Info.NRB_TOP=0x90;             // Nrb TOP=6                      (R36[7:4]=4'b1001)
+				   R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		   }
+	   }
+	        R848_SysFreq_Info.MIXER_TOP=0x04;	       // MIXER TOP=11               (R36[3:0]=4'b0100)
+			R848_SysFreq_Info.MIXER_VTH_L=0xB7;   // MIXER VTH/L=1.44/1.04  (R32=0xB7)
+			//R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+
+		break;
+
+	case R848_FM:
+		if((RF_freq>=300000)&&(RF_freq<=472000)) {
+			R848_SysFreq_Info.LNA_VTH_L=0xA4;	   // LNA VTH/L=1.34/0.74     (R31=0xA4)
+		} else {
+			R848_SysFreq_Info.LNA_VTH_L=0xA5;	   // LNA VTH/L=1.34/0.84     (R31=0xA5)
+		}
+		R848_SysFreq_Info.LNA_TOP=0x03;		       // LNA TOP=4                    (R35[2:0]=3'b011)
+		R848_SysFreq_Info.MIXER_TOP=0x05;	       // MIXER TOP=10               (R36[3:0]=4'b0100)
+		R848_SysFreq_Info.MIXER_VTH_L=0x95;   // MIXER VTH/L=1.24/0.84  (R32=0x95)
+		R848_SysFreq_Info.RF_TOP=0x60;               // RF TOP=4                        (R34[7:5]=3'b011)
+		R848_SysFreq_Info.NRB_TOP=0x20;            // Nrb TOP=13                       (R36[7:4]=4'b0010)
+		R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		break;
+
+	default: //DVB-T 8M
+		if((RF_freq>=300000)&&(RF_freq<=472000)) {
+			R848_SysFreq_Info.LNA_VTH_L=0xA4;	   // LNA VTH/L=1.34/0.74     (R31=0xA4)
+		} else {
+			R848_SysFreq_Info.LNA_VTH_L=0xA5;	   // LNA VTH/L=1.34/0.84     (R31=0xA5)
+		}
+		R848_SysFreq_Info.LNA_TOP=0x03;		       // LNA TOP=4                    (R35[2:0]=3'b011)
+		R848_SysFreq_Info.MIXER_TOP=0x05;	       // MIXER TOP=10               (R36[3:0]=4'b0100)
+		R848_SysFreq_Info.MIXER_VTH_L=0x95;   // MIXER VTH/L=1.24/0.84  (R32=0x95)
+		R848_SysFreq_Info.RF_TOP=0x40;               // RF TOP=5                        (R34[7:5]=3'b010)
+		R848_SysFreq_Info.NRB_TOP=0x20;            // Nrb TOP=13                       (R36[7:4]=4'b0010)
+		R848_SysFreq_Info.NRB_BW=0xC0;             // Nrb BW=lowest                  (R35[7:6]=2'b11)
+		break;
+	} //end switch
+
+	R848_SysFreq_Info.RF_FAST_DISCHARGE = 0x00;    //0 	 R848:R46[3:1]=3'b000
+	R848_SysFreq_Info.RF_SLOW_DISCHARGE = 0x80;    //4   R848:R22[7:5]=2'b100
+	R848_SysFreq_Info.RFPD_PLUSE_ENA = 0x10;	   //1   R848:R38[4]=1
+
+	R848_SysFreq_Info.LNA_FAST_DISCHARGE = 0x0A;    //10  R848:R43[4:0]=5'b01010
+	R848_SysFreq_Info.LNA_SLOW_DISCHARGE = 0x00;    //0  R848:R22[4:2]=3'b000
+	R848_SysFreq_Info.LNAPD_PLUSE_ENA = 0x00 ;	    //0  R848:R17[7]=0
+
+	//AGC Clk Rate
+	R848_SysFreq_Info.AGC_CLK = 0x00;              //1k   R26[4:2]  //default
+
+	//TF LPF setting
+	switch(R848_Standard) {
+		case R848_DTMB_4570:
+		case R848_DTMB_6000:
+		case R848_DTMB_6M_BW_IF_5M:
+		case R848_DTMB_6M_BW_IF_4500:
+		case R848_DTMB_IF_5M:
+			 //if(RF_freq<=196000)
+			//	 R848_SysFreq_Info.BYP_LPF = 0x40;		  //low pass R12[6]
+			 //else
+				 R848_SysFreq_Info.BYP_LPF = 0x00;      //bypass  R12[6]
+
+			break;
+		case R848_DVB_T_6M:
+		case R848_DVB_T_7M:
+		case R848_DVB_T_8M:
+		case R848_DVB_T_6M_IF_5M:
+		case R848_DVB_T_7M_IF_5M:
+		case R848_DVB_T_8M_IF_5M:
+		case R848_DVB_T2_6M:
+		case R848_DVB_T2_7M:
+		case R848_DVB_T2_8M:
+		case R848_DVB_T2_1_7M:
+		case R848_DVB_T2_10M:
+		case R848_DVB_T2_6M_IF_5M:
+		case R848_DVB_T2_7M_IF_5M:
+		case R848_DVB_T2_8M_IF_5M:
+		case R848_DVB_T2_1_7M_IF_5M:
+			if(RF_freq>=662000 && RF_freq<=670000) {
+				R848_SysFreq_Info.RF_SLOW_DISCHARGE = 0x20;    //1   R848:R22[7:5]=2'b001
+				R848_SysFreq_Info.AGC_CLK = 0x18;		 //60Hz   R26[4:2]
+			} else {
+				R848_SysFreq_Info.RF_SLOW_DISCHARGE = 0x80;    //4   R848:R22[7:5]=2'b100
+				R848_SysFreq_Info.AGC_CLK = 0x00;		 //1KHz   R26[4:2]
+				switch(R848_Standard) {
+					case R848_DVB_T2_6M:
+					case R848_DVB_T2_7M:
+					case R848_DVB_T2_8M:
+					case R848_DVB_T2_1_7M:
+					case R848_DVB_T2_10M:
+					case R848_DVB_T2_6M_IF_5M:
+					case R848_DVB_T2_7M_IF_5M:
+					case R848_DVB_T2_8M_IF_5M:
+					case R848_DVB_T2_1_7M_IF_5M:
+						R848_SysFreq_Info.AGC_CLK = 0x1C;		 //250Hz   R26[4:2]
+						break;
+				}
+			}
+		break;
+
+		default:  //other standard
+			if(RF_freq<=236000)
+				R848_SysFreq_Info.BYP_LPF = 0x40;      //low pass  R12[6]
+			else
+				R848_SysFreq_Info.BYP_LPF = 0x00;      //bypass  R12[6]
+
+			break;
+	} //end switch
+
+	return R848_SysFreq_Info;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+R848_ErrCode R848_RfGainMode( struct r848_priv *priv,R848_RF_Gain_TYPE R848_RfGainType)
+{
+	int ret;
+	u8 buf[5];
+
+    u8 MixerGain = 0;
+	u8 RfGain = 0;
+	u8 LnaGain = 0;
+	I2C_TYPE  R848_I2C;
+	I2C_LEN_TYPE R848_I2C_Len;
+
+	if(R848_RfGainType==RF_MANUAL)
+	{
+		//LNA auto off
+	     R848_I2C.RegAddr = 0x0D;
+	     priv->cfg->R848_Array[5] = priv->cfg->R848_Array[5] | 0x80;   // 848:13[7:0]   
+		 R848_I2C.Data = priv->cfg->R848_Array[5];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+		 //Mixer buffer off
+	     R848_I2C.RegAddr = 0x22;
+	     priv->cfg->R848_Array[26] = priv->cfg->R848_Array[26] | 0x10;  // 848:34[7:0]   
+		 R848_I2C.Data = priv->cfg->R848_Array[26];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+		 //Mixer auto off
+	     R848_I2C.RegAddr = 0x0F;
+	     priv->cfg->R848_Array[7] = priv->cfg->R848_Array[7] & 0xEF;  //848:15[6:0]
+		 R848_I2C.Data = priv->cfg->R848_Array[7];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+//		R848_I2C_Len.RegAddr = 0x00;
+//		R848_I2C_Len.Len     = 5; 
+//		if(I2C_Read_Len(priv,&R848_I2C_Len) != RT_Success)
+//		{
+//			I2C_Read_Len(priv,&R848_I2C_Len);
+//		}
+		ret = r848_rdm(priv, 0x00, buf, 5);
+		if (ret)
+			return ret;
+
+		//MixerGain = (((buf[1] & 0x40) >> 6)<<3)+((buf[3] & 0xE0)>>5);   //?
+		MixerGain = (buf[3] & 0x0F); //mixer // 848:3[4:0]
+		RfGain = ((buf[3] & 0xF0) >> 4);   //rf		 // 848:3[4:0] 
+		LnaGain = buf[4] & 0x1F;  //lna    // 848:4[4:0]  
+
+		//set LNA gain
+	     R848_I2C.RegAddr = 0x0D;
+	     priv->cfg->R848_Array[5] = (priv->cfg->R848_Array[5] & 0xE0) | LnaGain;  // 848:13[7:0]  
+		 R848_I2C.Data = priv->cfg->R848_Array[5];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+		 //set Mixer Buffer gain
+	     R848_I2C.RegAddr = 0x22;
+	     priv->cfg->R848_Array[26] = (priv->cfg->R848_Array[26] & 0xF0) | RfGain;  //848:34[7:0] 
+		 R848_I2C.Data = priv->cfg->R848_Array[26];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+		 //set Mixer gain
+	     R848_I2C.RegAddr = 0x0F;
+	     priv->cfg->R848_Array[7] = (priv->cfg->R848_Array[7] & 0xF0) | MixerGain; // 848:15[6:0]  
+		 R848_I2C.Data = priv->cfg->R848_Array[7];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+	}
+	else
+	{
+	    //LNA auto on
+	     R848_I2C.RegAddr = 0x0D;
+	     priv->cfg->R848_Array[5] = priv->cfg->R848_Array[5] & 0x7F;  // 848:13[7:0]  
+		 R848_I2C.Data = priv->cfg->R848_Array[5];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+		 //Mixer buffer on
+	     R848_I2C.RegAddr = 0x22;
+	     priv->cfg->R848_Array[26] = priv->cfg->R848_Array[26] & 0xEF;	// 848:34[7:0]  
+		 R848_I2C.Data = priv->cfg->R848_Array[26];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+
+		 //Mixer auto on
+	     R848_I2C.RegAddr = 0x0F;
+	     priv->cfg->R848_Array[7] = priv->cfg->R848_Array[7] | 0x10;	// 848:15[6:0]  
+		 R848_I2C.Data = priv->cfg->R848_Array[7];
+	     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		       return RT_Fail;
+	}
+
+    return RT_Success;
+}
+
+
+
+R848_ErrCode R848_TF_Check( struct r848_priv *priv)
+{
+	u32   RingVCO = 0;
+	u32   RingFreq = 72000;
+	u32   RingRef = R848_Xtal;
+	u8     divnum_ring = 0;
+	I2C_TYPE  R848_I2C;
+	 u8   VGA_Count = 0;
+	 u8   VGA_Read = 0;
+
+	if(R848_Xtal==16000)  //16M
+	{
+         divnum_ring = 11;
+	}
+	else  //24M
+	{
+		 divnum_ring = 2;
+	}
+	 RingVCO = (16+divnum_ring)* 8 * RingRef;
+	 RingFreq = RingVCO/48;
+
+	 if(R848_Cal_Prepare(priv,R848_TF_LNA_CAL) != RT_Success)      
+	      return RT_Fail;
+
+
+     R848_I2C.RegAddr = 0x27;	
+     priv->cfg->R848_Array[31] = (priv->cfg->R848_Array[31] & 0x03) | 0x80 | (divnum_ring<<2);  //pre div=6 & div_num
+     R848_I2C.Data = priv->cfg->R848_Array[31];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	 //Ring PLL PW on
+	 R848_I2C.RegAddr = 0x12;	
+     priv->cfg->R848_Array[18] = (priv->cfg->R848_Array[18] & 0xEF); 
+     R848_I2C.Data = priv->cfg->R848_Array[18];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	 //NAT Det Sour : Mixer buf out
+	 R848_I2C.RegAddr = 0x25;	
+     priv->cfg->R848_Array[37] = (priv->cfg->R848_Array[37] & 0x7F); 
+     R848_I2C.Data = priv->cfg->R848_Array[37];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+
+
+	 //R848 R33[7:0]   
+
+	 priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] & 0x00) | 0x8B;  //out div=8, RF poly=low band, power=min_lp
+	 if(RingVCO>=3200000)
+	    priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] & 0xDF);      //vco_band=high, R25[5]=0
+	 else
+        priv->cfg->R848_Array[25] = (priv->cfg->R848_Array[25] | 0x20);      //vco_band=low, R25[5]=1
+	 R848_I2C.RegAddr = 0x21;
+	 R848_I2C.Data = priv->cfg->R848_Array[25];
+	 if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;	
+
+     //Must do before PLL()
+	 if(R848_MUX(priv,RingFreq + 5000, RingFreq, R848_STD_SIZE) != RT_Success)     //FilCal MUX (LO_Freq, RF_Freq)
+	     return RT_Fail;
+
+	 //Set PLL
+	 if(R848_PLL(priv,(RingFreq + 5000), R848_STD_SIZE) != RT_Success)   //FilCal PLL
+	       return RT_Fail;
+
+
+	//Set LNA TF=(1,15),for VGA training   // R848 R8[6:0]
+	 R848_I2C.RegAddr = 0x08;
+     priv->cfg->R848_Array[0] = (priv->cfg->R848_Array[0] & 0x80) | 0x1F;  	
+     R848_I2C.Data = priv->cfg->R848_Array[0];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+	//Qctrl=off  // R848 R14[5] 
+	 R848_I2C.RegAddr = 0x0E;
+     priv->cfg->R848_Array[6] = (priv->cfg->R848_Array[6] & 0xDF);  	
+     R848_I2C.Data = priv->cfg->R848_Array[6];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+
+	// FilterComp OFF  // R848 R14[2]  
+	 R848_I2C.RegAddr = 0x0E;
+     priv->cfg->R848_Array[6] = (priv->cfg->R848_Array[6] & 0xFB);  	
+     R848_I2C.Data = priv->cfg->R848_Array[6];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+
+	// Byp-LPF: Bypass  R848 R12[6]  12-8=4  12(0x0C) is addr ; [4] is data
+	 R848_I2C.RegAddr = 0x0C;
+     priv->cfg->R848_Array[4] = priv->cfg->R848_Array[4] & 0xBF;  	
+     R848_I2C.Data = priv->cfg->R848_Array[4];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+
+
+	 //Adc=on; Vga code mode, Gain = -12dB 
+	 //R848 R20[3:0]         set 0
+	 //R848 R9[1]            set 1
+	 //R848 R11[3]           set 0
+	 //R848 R18[7]           set 0
+	 //R848 R15[7]           set 0
+	 
+	 // VGA Gain = -12dB 
+     R848_I2C.RegAddr = 0x14;
+     priv->cfg->R848_Array[12] = (priv->cfg->R848_Array[12] & 0xF0);
+     R848_I2C.Data = priv->cfg->R848_Array[12];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	// Vga code mode
+     R848_I2C.RegAddr = 0x09;
+     priv->cfg->R848_Array[1] = (priv->cfg->R848_Array[1] | 0x02);
+     R848_I2C.Data = priv->cfg->R848_Array[1];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	// VGA 6dB
+     R848_I2C.RegAddr = 0x0B;
+     priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xF7);
+     R848_I2C.Data = priv->cfg->R848_Array[3];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	// VGA PW ON
+     R848_I2C.RegAddr = 0x12;
+     priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0x7F);
+     R848_I2C.Data = priv->cfg->R848_Array[10];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+	 // Adc on
+     R848_I2C.RegAddr = 0x0F;
+     priv->cfg->R848_Array[7] = (priv->cfg->R848_Array[7] & 0x7F);
+     R848_I2C.Data = priv->cfg->R848_Array[7];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+           return RT_Fail;
+
+
+
+	 //------- increase VGA power to let ADC read value significant ---------//
+
+
+	 for(VGA_Count=0; VGA_Count < 16; VGA_Count ++)
+	 {
+		R848_I2C.RegAddr = 0x14;
+		R848_I2C.Data = (priv->cfg->R848_Array[12] & 0xF0) + VGA_Count;  
+		if(I2C_Write(priv,&R848_I2C) != RT_Success)
+			return RT_Fail;
+
+		msleep(10); //
+		
+		if(R848_Muti_Read(priv,&VGA_Read) != RT_Success)
+			return RT_Fail;
+
+		if(VGA_Read > 40)
+			break;
+	 }
+
+	 //Set LNA TF=(0,0)
+	 R848_I2C.RegAddr = 0x08;
+     priv->cfg->R848_Array[0] =(priv->cfg->R848_Array[0] & 0x80);  	
+     R848_I2C.Data = priv->cfg->R848_Array[0];
+     if(I2C_Write(priv,&R848_I2C) != RT_Success)
+          return RT_Fail;
+
+	 msleep(10); //
+
+	 if(R848_Muti_Read(priv,&VGA_Read) != RT_Success)
+		  return RT_Fail;
+
+	 if(VGA_Read > (36))
+        priv->cfg->R848_DetectTfType = R848_UL_USING_BEAD;
+	 else
+	    priv->cfg->R848_DetectTfType = R848_UL_USING_270NH;
+
+	return RT_Success;
+}
+
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+
+R848_ErrCode R848_SetStandard(struct r848_priv *priv,R848_Standard_Type RT_Standard)
+{
+	I2C_TYPE  R848_I2C;
+	int i=0;
+
+	// Filter Calibration
+	u8 u1FilCalGap = 8;
+
+
+	u8 R848_Fil_Cal_flag[R848_STD_SIZE];
+	u8 R848_Fil_Cal_BW[R848_STD_SIZE];
+	u8 R848_Fil_Cal_code[R848_STD_SIZE];
+
+	for (i=0; i<R848_STD_SIZE; i++) {
+		R848_Fil_Cal_flag[i] = 1;
+		R848_Fil_Cal_code[i] = 0;
+		R848_Fil_Cal_BW[i] = 0x00;
+	}
+
+	if(RT_Standard != priv->cfg->R848_pre_standard)
+	{
+		 if(R848_InitReg(priv,RT_Standard) != RT_Success)
+		     return RT_Fail;
+	}
+
+	priv->cfg->Sys_Info1 = R848_Sys_Sel(priv, RT_Standard);
+
+	// Filter Calibration
+
+
+   if(R848_Fil_Cal_flag[RT_Standard] == 1)
+	{
+		R848_Fil_Cal_code[RT_Standard] = R848_Filt_Cal_ADC(priv, priv->cfg->Sys_Info1.FILT_CAL_IF, priv->cfg->Sys_Info1.BW, u1FilCalGap);
+		R848_Fil_Cal_BW[RT_Standard] = 0;// R848_Bandwidth;
+        R848_Fil_Cal_flag[RT_Standard] = 0;
+
+	    //Reset register and Array 
+	    if(R848_InitReg(priv, RT_Standard) != RT_Success)        
+		   return RT_Fail;
+	}
+
+	// Set Filter Auto Ext
+	R848_I2C.RegAddr = 0x13;	// R19[4]  
+	priv->cfg->R848_Array[11] = (priv->cfg->R848_Array[11] & 0xEF) | priv->cfg->Sys_Info1.FILT_EXT_ENA;  
+	R848_I2C.Data = priv->cfg->R848_Array[11];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+
+	if(priv->cfg->Sys_Info1.FILT_EXT_ENA==0x10)  //(%)
+	{
+		
+			 if(R848_Fil_Cal_code[RT_Standard]< 2)  
+			   R848_Fil_Cal_code[RT_Standard] = 2;
+		
+			 if((priv->cfg->Sys_Info1.FILT_EXT_POINT & 0x02)==0x02)  //HPF+3
+			 {
+				  if(priv->cfg->Sys_Info1.HPF_COR>12)  
+				  {    priv->cfg->Sys_Info1.HPF_COR = 12; }
+			 }
+			 else  //HPF+1
+			 {
+				  if(priv->cfg->Sys_Info1.HPF_COR>14)  
+				  {    priv->cfg->Sys_Info1.HPF_COR = 15; }		 
+			 }		  			
+	}
+
+
+	// Set LPF fine code
+	R848_I2C.RegAddr = 0x12;	//  R848:R18[3:0]  
+	priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0xF0) | R848_Fil_Cal_code[RT_Standard];  
+	R848_I2C.Data = priv->cfg->R848_Array[10];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set LPF coarse BW
+	R848_I2C.RegAddr = 0x13;	// R848:R19[6:5]  
+	priv->cfg->R848_Array[11] = (priv->cfg->R848_Array[11] & 0x9F) | R848_Fil_Cal_BW[RT_Standard];
+	R848_I2C.Data = priv->cfg->R848_Array[11];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+	
+	// Set HPF corner & 1.7M mode
+	R848_I2C.RegAddr = 0x13;	//R848:R19[7 & 3:0]  
+	priv->cfg->R848_Array[11] = (priv->cfg->R848_Array[11] & 0x70) | priv->cfg->Sys_Info1.HPF_COR | priv->cfg->Sys_Info1.V17M;
+	R848_I2C.Data = priv->cfg->R848_Array[11];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set TF current 
+	R848_I2C.RegAddr = 0x0B;	//  R848:R11[6]  
+	priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] & 0xBF) | priv->cfg->Sys_Info1.TF_CUR;  
+	R848_I2C.Data = priv->cfg->R848_Array[3];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set Filter current 
+	R848_I2C.RegAddr = 0x12;	//  R848:R18[6:5]  
+	priv->cfg->R848_Array[10] = (priv->cfg->R848_Array[10] & 0x9F) | priv->cfg->Sys_Info1.FILT_CUR;  
+	//R848_Array[10] = (R848_Array[10] & 0x9F) | 0x60;   //lowest
+	R848_I2C.Data = priv->cfg->R848_Array[10];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set Switch Buffer current 
+	R848_I2C.RegAddr = 0x0C;	//  R848:R12[2] 
+	priv->cfg->R848_Array[4] = (priv->cfg->R848_Array[4] & 0xFB) | priv->cfg->Sys_Info1.SWBUF_CUR;   
+	R848_I2C.Data = priv->cfg->R848_Array[4];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set Filter Comp 
+	R848_I2C.RegAddr = 0x26;	//  R848:R38[6:5]  
+	priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0x9F) | priv->cfg->Sys_Info1.FILT_COMP;  
+	R848_I2C.Data = priv->cfg->R848_Array[30];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+   // Set Filter 3dB
+	R848_I2C.RegAddr = 0x26;	// R848:R38[7]  
+	priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0xF7) | priv->cfg->Sys_Info1.FILT_3DB;  
+	R848_I2C.Data = priv->cfg->R848_Array[30];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set Filter Ext Condition (%)
+	R848_I2C.RegAddr = 0x26;	//  R848:R38[2:0] 
+    priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0xF8) | 0x04 | priv->cfg->Sys_Info1.FILT_EXT_POINT;   //ext both HPF/LPF
+	R848_I2C.Data = priv->cfg->R848_Array[30];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+/*
+	// Set Inductor Bias
+	R848_I2C.RegAddr = 0x04;
+	R848_Array[4] = (R848_Array[4] & 0xFE) | Sys_Info1.INDUC_BIAS; 
+	R848_I2C.Data = R848_Array[4];
+	if(I2C_Write(&R848_I2C) != RT_Success)
+		return RT_Fail;
+*/
+	// Set sw cap clk
+	R848_I2C.RegAddr = 0x1A;	//  R848:R26[1:0]  
+	priv->cfg->R848_Array[18] = (priv->cfg->R848_Array[18] & 0xFC) | priv->cfg->Sys_Info1.SWCAP_CLK; 
+	R848_I2C.Data = priv->cfg->R848_Array[18];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set NA det power
+	R848_I2C.RegAddr = 0x26;	// R848:R38[7] 
+	priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0x7F) | priv->cfg->Sys_Info1.NA_PWR_DET; 
+	R848_I2C.Data = priv->cfg->R848_Array[30];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+/*
+	// Set AGC clk 
+	R848_I2C.RegAddr = 0x1A;	//  R848:R26[4:2] 
+	R848_Array[18] = (R848_Array[18] & 0xE3) | Sys_Info1.AGC_CLK;  
+	R848_I2C.Data = R848_Array[18];
+	if(I2C_Write(&R848_I2C) != RT_Success)
+		return RT_Fail;
+*/
+
+	//Set GPO High
+	R848_I2C.RegAddr = 0x17;	// R848:R23[4:2]  
+	priv->cfg->R848_Array[15] = (priv->cfg->R848_Array[15] & 0xFE) | 0x01;
+	R848_I2C.Data = priv->cfg->R848_Array[15];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+	return RT_Fail;
+
+
+	return RT_Success;
+}
+
+
+
+R848_ErrCode R848_SetFrequency(struct r848_priv *priv,R848_Set_Info R848_INFO)
+{
+	u32	LO_KHz;
+	I2C_TYPE  R848_I2C;
+	R848_SysFreq_Info_Type	SysFreq_Info1;
+
+	if(R848_INFO.R848_Standard!=R848_DVB_S) {
+		// Check Input Frequency Range
+		if((R848_INFO.RF_KHz<40000) || (R848_INFO.RF_KHz>1002000))
+		{
+			return RT_Fail;
+		}
+	} else {
+		// Check Input Frequency Range
+		if((R848_INFO.RF_KHz<40000) || (R848_INFO.RF_KHz>2400000)) {
+			return RT_Fail;
+		}
+	}
+
+	LO_KHz = R848_INFO.RF_KHz + priv->cfg->Sys_Info1.IF_KHz;
+
+	//Set MUX dependent var. Must do before PLL( )
+	if(R848_MUX(priv,LO_KHz, R848_INFO.RF_KHz, R848_INFO.R848_Standard) != RT_Success)   //normal MUX
+		return RT_Fail;
+
+	//Set PLL
+	if(R848_PLL(priv,LO_KHz, R848_INFO.R848_Standard) != RT_Success) //noraml PLL
+		return RT_Fail;
+
+	//Set TF
+	if(R848_SetTF(priv,R848_INFO.RF_KHz, priv->cfg->R848_SetTfType) != RT_Success)
+		return RT_Fail;
+
+	//R848_IMR_point_num = Freq_Info1.IMR_MEM;
+
+	//Q1.5K   Q_ctrl  R848:R14[4]
+	//if(R848_INFO.RF_KHz<R848_LNA_MID_LOW[R848_TF_NARROW]) //<300MHz
+	//	R848_Array[6] = R848_Array[6] | 0x10;
+	//else
+	//	R848_Array[6] = R848_Array[6] & 0xEF;
+
+	if(R848_INFO.RF_KHz<=472000) //<472MHz
+		priv->cfg->R848_Array[6] = priv->cfg->R848_Array[6] | 0x10;
+	else
+		priv->cfg->R848_Array[6] = priv->cfg->R848_Array[6] & 0xEF;
+
+	//medQctrl 1.5K
+	if((R848_INFO.RF_KHz>=300000)&&(R848_INFO.RF_KHz<=472000)) //<473MHz and >299MHz
+		priv->cfg->R848_Array[6] = priv->cfg->R848_Array[6] | 0x01;
+	else
+	 	priv->cfg->R848_Array[6] = priv->cfg->R848_Array[6] & 0xFE;
+
+	R848_I2C.RegAddr = 0x0E;	//  R848:R14[1]
+	R848_I2C.Data = priv->cfg->R848_Array[6];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	//3~6 shrink
+	if((R848_INFO.RF_KHz>=300000)&&(R848_INFO.RF_KHz<=550000)) //<551MHz and >299MHz
+		priv->cfg->R848_Array[3] = priv->cfg->R848_Array[3] & 0xFB;
+	else
+		priv->cfg->R848_Array[3] = priv->cfg->R848_Array[3] | 0x04;
+
+	R848_I2C.RegAddr = 0x0B;	//  R848:R11[2]
+	R848_I2C.Data = priv->cfg->R848_Array[3];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	//set Xtal AAC on=1 ;off=0
+	R848_I2C.RegAddr = 0x18;	//  R848:R24[1]
+	priv->cfg->R848_Array[16] = priv->cfg->R848_Array[16] & 0xFD;
+	R848_I2C.Data = priv->cfg->R848_Array[16];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+
+	//Get Sys-Freq parameter
+	SysFreq_Info1 = R848_SysFreq_Sel(priv, R848_INFO.R848_Standard, R848_INFO.RF_KHz);
+
+	// Set LNA_TOP
+	R848_I2C.RegAddr = 0x23;	//  R848:R35[2:0]
+	priv->cfg->R848_Array[27] = (priv->cfg->R848_Array[27] & 0xF8) | (SysFreq_Info1.LNA_TOP);
+	R848_I2C.Data = priv->cfg->R848_Array[27];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+        	return RT_Fail;
+
+	// Set LNA VTHL
+	R848_I2C.RegAddr = 0x1F;	// R848:R31[7:0]
+	priv->cfg->R848_Array[23] = (priv->cfg->R848_Array[23] & 0x00) | SysFreq_Info1.LNA_VTH_L;
+	R848_I2C.Data = priv->cfg->R848_Array[23];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set MIXER TOP
+	R848_I2C.RegAddr = 0x24;	// R848:R36[7:0]
+	priv->cfg->R848_Array[28] = (priv->cfg->R848_Array[28] & 0xF0) | (SysFreq_Info1.MIXER_TOP);
+	R848_I2C.Data = priv->cfg->R848_Array[28];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set MIXER VTHL
+	R848_I2C.RegAddr = 0x20;	//  R848:R32[7:0]
+	priv->cfg->R848_Array[24] = (priv->cfg->R848_Array[24] & 0x00) | SysFreq_Info1.MIXER_VTH_L;
+	R848_I2C.Data = priv->cfg->R848_Array[24];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set RF TOP
+	R848_I2C.RegAddr = 0x22;	// R848:R34[7:0]
+	priv->cfg->R848_Array[26] = (priv->cfg->R848_Array[26] & 0x1F) | SysFreq_Info1.RF_TOP;
+	R848_I2C.Data = priv->cfg->R848_Array[26];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set Nrb TOP
+	R848_I2C.RegAddr = 0x24;	//R848:R36[7:4]
+	priv->cfg->R848_Array[28] = (priv->cfg->R848_Array[28] & 0x0F) | SysFreq_Info1.NRB_TOP;
+	R848_I2C.Data = priv->cfg->R848_Array[28];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set Nrb BW
+	R848_I2C.RegAddr = 0x23;	//  R848:R35[7:6]
+	priv->cfg->R848_Array[27] = (priv->cfg->R848_Array[27] & 0x3F) | SysFreq_Info1.NRB_BW;
+	R848_I2C.Data = priv->cfg->R848_Array[27];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set TF LPF
+	R848_I2C.RegAddr = 0x0C;	// R848:R12[6]
+	priv->cfg->R848_Array[4] = (priv->cfg->R848_Array[4] & 0xBF) | SysFreq_Info1.BYP_LPF;
+	R848_I2C.Data = priv->cfg->R848_Array[4];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	R848_I2C.RegAddr = 0x2E;	//0 	 R848:R46[3:1]=0'b000
+	priv->cfg->R848_Array[38] = (priv->cfg->R848_Array[38] & 0xF1) | SysFreq_Info1.RF_FAST_DISCHARGE;
+	R848_I2C.Data = priv->cfg->R848_Array[38];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	R848_I2C.RegAddr = 0x16;	//4   R848:R22[7:5]=2'b010
+	priv->cfg->R848_Array[14] = (priv->cfg->R848_Array[14] & 0x1F) | SysFreq_Info1.RF_SLOW_DISCHARGE;
+	R848_I2C.Data = priv->cfg->R848_Array[14];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	R848_I2C.RegAddr = 0x26;	//1   R848:R38[4]=1
+	priv->cfg->R848_Array[30] = (priv->cfg->R848_Array[30] & 0xEF) | SysFreq_Info1.RFPD_PLUSE_ENA;
+	R848_I2C.Data = priv->cfg->R848_Array[30];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	R848_I2C.RegAddr = 0x2B;	//10  R848:R43[4:0]=5'b01010
+	priv->cfg->R848_Array[35] = (priv->cfg->R848_Array[35] & 0xE0) | SysFreq_Info1.LNA_FAST_DISCHARGE;
+	R848_I2C.Data = priv->cfg->R848_Array[35];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	R848_I2C.RegAddr = 0x16;	//0  R848:R22[4:2]=3'b000
+	priv->cfg->R848_Array[14] = (priv->cfg->R848_Array[14] & 0xE3) | SysFreq_Info1.LNA_SLOW_DISCHARGE;
+	R848_I2C.Data = priv->cfg->R848_Array[14];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	R848_I2C.RegAddr = 0x11;	//1  R848:R17[7]=0
+	priv->cfg->R848_Array[9] = (priv->cfg->R848_Array[9] & 0x7F) | SysFreq_Info1.LNAPD_PLUSE_ENA;
+	R848_I2C.Data = priv->cfg->R848_Array[9];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	// Set AGC clk
+	R848_I2C.RegAddr = 0x1A;	//  R848:R26[4:2]
+	priv->cfg->R848_Array[18] = (priv->cfg->R848_Array[18] & 0xE3) | SysFreq_Info1.AGC_CLK;
+	R848_I2C.Data = priv->cfg->R848_Array[18];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+	//no clk out
+	R848_I2C.RegAddr = 0x19;
+	priv->cfg->R848_Array[17] = (priv->cfg->R848_Array[17] | 0x80);   //no clk out // R848:R25[7]
+	R848_I2C.Data = priv->cfg->R848_Array[17];
+	if(I2C_Write(priv,&R848_I2C) != RT_Success)
+		return RT_Fail;
+
+
+	//for DVB-T2
+        switch(R848_INFO.R848_Standard) {
+		case R848_DVB_T2_6M:
+		case R848_DVB_T2_7M:
+		case R848_DVB_T2_8M:
+		case R848_DVB_T2_1_7M:
+		case R848_DVB_T2_10M:
+		case R848_DVB_T2_6M_IF_5M:
+		case R848_DVB_T2_7M_IF_5M:
+		case R848_DVB_T2_8M_IF_5M:
+		case R848_DVB_T2_1_7M_IF_5M:
+			msleep(100);
+			/*
+			//AGC clk 250Hz
+			R848_I2C.RegAddr = 0x1A;	//  R26[4:2]
+			R848_Array[18] = (R848_Array[18] & 0xE3) | 0x1C;  //[4:2]=111
+			R848_I2C.Data = R848_Array[18];
+			if(I2C_Write(&R848_I2C) != RT_Success)
+				 return RT_Fail;
+			*/
+
+			//force plain mode
+			R848_I2C.RegAddr = 0x0B;	// R848:R11[7]
+			priv->cfg->R848_Array[3] = (priv->cfg->R848_Array[3] | 0x80);  //[7]=1
+			R848_I2C.Data = priv->cfg->R848_Array[3];
+			if(I2C_Write(priv,&R848_I2C) != RT_Success)
+				return RT_Fail;
+
+			R848_I2C.RegAddr = 0x0A;	// R848:R10[5]
+			priv->cfg->R848_Array[2] = (priv->cfg->R848_Array[2] & 0xDF);  //[5]=0
+			R848_I2C.Data = priv->cfg->R848_Array[2];
+			if(I2C_Write(priv,&R848_I2C) != RT_Success)
+				return RT_Fail;
+
+			break;
+		default:
+			break;
+	}//end switch
+
+	return RT_Success;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+static int r848_release(struct dvb_frontend *fe)
+{
+	struct r848_priv *priv = fe->tuner_priv;
+	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
+
+	kfree(fe->tuner_priv);
+	fe->tuner_priv = NULL;
+	return 0;
+}
+
+static int r848_init(struct dvb_frontend *fe)
+{
+	struct r848_priv *priv = fe->tuner_priv;
+	int ret;
+	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
+
+	u8 i;
+
+	printk("init tuner\n");
+
+	if (priv->inited == 1)
+		return 0;
+
+	priv->inited = 1;
+
+	printk("init tuner first time\n");
+
+	if(R848_InitReg(priv,R848_STD_SIZE) != RT_Success)
+		return RT_Fail;
+
+	if(R848_TF_Check(priv) != RT_Success)
+		return RT_Fail;
+
+	//start IMR calibration
+	if(R848_InitReg(priv,R848_STD_SIZE) != RT_Success)        //write initial reg before doing IMR Cal
+		return RT_Fail;
+
+	if(R848_Cal_Prepare(priv,R848_IMR_CAL) != RT_Success)
+		return RT_Fail;
+
+	if(R848_IMR(priv,3, 0) != RT_Success)       //Full K node 3
+		return RT_Fail;
+
+	if(R848_IMR(priv,0, 1) != RT_Success)
+		return RT_Fail;
+
+	if(R848_IMR(priv,1, 1) != RT_Success)
+		return RT_Fail;
+
+	if(R848_IMR(priv,2, 1) != RT_Success)
+		return RT_Fail;
+
+	if(R848_IMR(priv,4, 0) != RT_Success)   //Full K node 4
+		return RT_Fail;
+
+	//do Xtal check
+	if(R848_InitReg(priv,R848_STD_SIZE) != RT_Success)
+		return RT_Fail;
+
+	priv->cfg->R848_Xtal_Pwr = XTAL_SMALL_LOWEST;
+	priv->cfg->R848_Xtal_Pwr_tmp = XTAL_SMALL_LOWEST;
+
+	for (i=0; i<3; i++) {
+		if(R848_Xtal_Check(priv) != RT_Success)
+			return RT_Fail;
+
+		if(priv->cfg->R848_Xtal_Pwr_tmp > priv->cfg->R848_Xtal_Pwr)
+			priv->cfg->R848_Xtal_Pwr = priv->cfg->R848_Xtal_Pwr_tmp;
+	}
+
+	//write initial reg
+	if(R848_InitReg(priv,R848_STD_SIZE) != RT_Success)
+		return RT_Fail;
+
+	priv->cfg->R848_pre_standard = R848_STD_SIZE;
+
+	ret = 0;
+
+	if (ret)
+		dev_dbg(&priv->i2c->dev, "%s() failed\n", __func__);
+
+	printk("init tuner done\n");
+	return ret;
+}
+
+static int r848_sleep(struct dvb_frontend *fe)
+{
+	struct r848_priv *priv = fe->tuner_priv;
+	int ret = 0;
+	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
+
+	//if (ret)
+	//	dev_dbg(&priv->i2c->dev, "%s() failed\n", __func__);
+	return ret;
+}
+
+static int r848_set_params(struct dvb_frontend *fe)
+{
+	struct r848_priv *priv = fe->tuner_priv;
+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+	int ret = 0, i;
+	u8 tuner_lock;
+
+	R848_Set_Info R848_INFO;
+
+	dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d frequency=%d " \
+			"symbol_rate=%d bandwidth_hz=%d\n", __func__,
+			c->delivery_system, c->frequency, c->symbol_rate,
+			c->bandwidth_hz);
+
+
+	/* failsafe */
+	R848_INFO.R848_Standard = R848_DVB_T2_8M_IF_5M;
+
+	switch (c->delivery_system) {
+	case SYS_DVBC_ANNEX_A:
+		R848_INFO.RF_KHz = c->frequency / 1000;
+		if(c->bandwidth_hz <= 6000000) {
+        		R848_INFO.R848_Standard = R848_DVB_C_6M_IF_5M;
+		} else if (c->bandwidth_hz <= 8000000) {
+			R848_INFO.R848_Standard = R848_DVB_C_8M_IF_5M;
+		}
+
+		/* set pll data */
+		if(R848_SetStandard(priv, R848_INFO.R848_Standard) != RT_Success) {
+			return RT_Fail;
+		}
+		if(R848_SetFrequency(priv, R848_INFO) != RT_Success) {
+			return RT_Fail;
+		}
+		break;
+	case SYS_DVBS:
+	case SYS_DVBS2:
+		R848_INFO.RF_KHz = c->frequency;
+		R848_INFO.R848_Standard = R848_DVB_S;
+		R848_INFO.DVBS_BW = (c->symbol_rate/200*135+2000000)/1000*2;//unit KHz
+		R848_INFO.R848_DVBS_OutputSignal_Mode = DIFFERENTIALOUT;
+		R848_INFO.R848_DVBS_AGC_Mode = AGC_NEGATIVE;
+
+		/* set pll data */
+		if(R848_DVBS_Setting(priv,R848_INFO) != RT_Success)
+			return RT_Fail;
+		break;
+	case SYS_DVBT:
+	case SYS_DVBT2:
+	default:
+		R848_INFO.RF_KHz = c->frequency / 1000;
+		if(c->bandwidth_hz <= 1700000) {
+			R848_INFO.R848_Standard = R848_DVB_T2_1_7M_IF_5M;
+		} else if (c->bandwidth_hz <= 6000000) {
+			R848_INFO.R848_Standard = R848_DVB_T2_6M_IF_5M;
+		} else if (c->bandwidth_hz <= 7000000) {
+			R848_INFO.R848_Standard = R848_DVB_T2_7M_IF_5M;
+		} else { //if(c->bandwidth_hz == 8000000) {
+			R848_INFO.R848_Standard = R848_DVB_T2_8M_IF_5M;
+		}
+
+		/* set pll data */
+		if(R848_SetStandard(priv, R848_INFO.R848_Standard) != RT_Success) {
+			return RT_Fail;
+		}
+		if(R848_SetFrequency(priv, R848_INFO) != RT_Success) {
+			return RT_Fail;
+		}
+		break;
+	}
+
+
+
+
+
+	if (ret) {
+		printk("[r848_lock_n_wait] Tuner lock function Failed!\n");
+		goto exit;
+	}
+	for (i = 0; i < 5; i++) {
+		ret = r848_get_lock_status(priv, &tuner_lock);
+		if(tuner_lock) {
+			printk("Tuner Locked.\n");
+			break;
+		} else {
+			printk("Tuner not Locked!\n");
+		}
+		msleep(20);
+	}
+
+exit:
+	return ret;
+}
+
+static const struct dvb_tuner_ops r848_tuner_ops = {
+	.info = {
+		.name           = "Rafael R848",
+
+//		.frequency_min  = 850000,
+//		.frequency_max  = 2300000,
+//		.frequency_step = 206,
+	},
+
+	.release = r848_release,
+
+	.init = r848_init,
+	.sleep = r848_sleep,
+	.set_params = r848_set_params,
+};
+
+struct dvb_frontend *r848_attach(struct dvb_frontend *fe,
+		struct r848_config *cfg, struct i2c_adapter *i2c)
+{
+	struct r848_priv *priv = NULL;
+
+	priv = kzalloc(sizeof(struct r848_priv), GFP_KERNEL);
+	if (priv == NULL) {
+		dev_dbg(&i2c->dev, "%s() attach failed\n", __func__);
+		return NULL;
+	}
+
+	priv->cfg = cfg;
+	priv->i2c = i2c;
+	priv->inited = 0;
+
+	dev_info(&priv->i2c->dev,
+		"%s: Rafael R848 successfully attached\n",
+		KBUILD_MODNAME);
+
+	memcpy(&fe->ops.tuner_ops, &r848_tuner_ops,
+			sizeof(struct dvb_tuner_ops));
+
+	fe->tuner_priv = priv;
+	return fe;
+}
+EXPORT_SYMBOL(r848_attach);
+
+MODULE_DESCRIPTION("Rafael R848 silicon tuner driver");
+MODULE_AUTHOR("Luis Alves <ljalvs@gmail.com>");
+MODULE_LICENSE("GPL");
diff -rpuN a/drivers/media/common/tuners/r848.h b/drivers/media/common/tuners/r848.h
--- a/drivers/media/common/tuners/r848.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/common/tuners/r848.h	2016-04-09 10:31:21.248007861 -0300
@@ -0,0 +1,85 @@
+/*
+ * Rafael R848 silicon tuner driver
+ *
+ * Copyright (C) 2015 Luis Alves <ljalvs@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License along
+ *    with this program; if not, write to the Free Software Foundation, Inc.,
+ *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef R848_H
+#define R848_H
+
+#include <linux/kconfig.h>
+#include "dvb_frontend.h"
+
+
+
+
+typedef struct _R848_Sys_Info_Type
+{
+	u16		   IF_KHz;
+	u16		   FILT_CAL_IF;
+	u8          BW;
+	u8		   V17M; 
+	u8		   HPF_COR;
+	u8          FILT_EXT_ENA;
+	u8          FILT_EXT_WIDEST;
+	u8          FILT_EXT_POINT;
+//	u8          AGC_CLK;
+	u8		   FILT_COMP;
+	u8		   FILT_CUR;  
+	u8		   FILT_3DB; 
+	u8		   SWBUF_CUR;  
+	u8          TF_CUR;              
+	u8		   INDUC_BIAS;  
+	u8          SWCAP_CLK;
+	u8		   NA_PWR_DET;  
+}R848_Sys_Info_Type;
+
+
+
+
+struct r848_config {
+	/* tuner i2c address */
+	u8 i2c_address;
+
+	// tuner
+	u8 R848_DetectTfType ;
+	unsigned char R848_pre_standard;
+	u8 R848_Array[40];
+	u8 R848_Xtal_Pwr ;
+	u8 R848_Xtal_Pwr_tmp ;
+
+  /* dvbc/t */
+u8 R848_SetTfType;
+	R848_Sys_Info_Type Sys_Info1;
+  /* DVBT */
+
+
+};
+
+#if IS_ENABLED(CONFIG_MEDIA_TUNER_R848)
+extern struct dvb_frontend *r848_attach(struct dvb_frontend *fe,
+		struct r848_config *cfg, struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend *r848_attach(struct dvb_frontend *fe,
+		struct r848_config *cfg, struct i2c_adapter *i2c)
+{
+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+	return NULL;
+}
+#endif
+
+#endif /* R848_H */
diff -rpuN a/drivers/media/common/tuners/r848_priv.h b/drivers/media/common/tuners/r848_priv.h
--- a/drivers/media/common/tuners/r848_priv.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/common/tuners/r848_priv.h	2016-04-09 10:31:21.252007846 -0300
@@ -0,0 +1,440 @@
+/*
+ * Rafael R848 silicon tuner driver
+ *
+ * Copyright (C) 2015 Luis Alves <ljalvs@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License along
+ *    with this program; if not, write to the Free Software Foundation, Inc.,
+ *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef R848_PRIV_H
+#define R848_PRIV_H
+
+struct r848_priv {
+	struct r848_config *cfg;
+	struct i2c_adapter *i2c;
+	u8 inited;
+};
+
+
+
+
+/* R848 */
+
+typedef struct _R848_I2C_LEN_TYPE
+{
+	u8 RegAddr;
+	u8 Data[50];
+	u8 Len;
+}I2C_LEN_TYPE;
+
+typedef struct _R848_I2C_TYPE
+{
+	u8 RegAddr;
+	u8 Data;
+}I2C_TYPE;
+//----------------------------------------------------------//
+//                   Define                                 //
+//----------------------------------------------------------//
+#define FOR_TDA10024    0
+
+#define VERSION   "R848_GUI_2.3A"
+
+#define R848_REG_NUM         40
+#define R848_TF_HIGH_NUM  8  
+#define R848_TF_MID_NUM    8
+#define R848_TF_LOW_NUM   8
+#define R848_TF_LOWEST_NUM   8
+#define R848_RING_POWER_FREQ_LOW  115000
+#define R848_RING_POWER_FREQ_HIGH 450000
+#define R848_IMR_IF              5300         
+#define R848_IMR_TRIAL       9
+#define R848_Xtal	                   16000
+//----------------------------------------------------------//
+//                   Internal Structure                            //
+//----------------------------------------------------------//
+
+
+typedef struct _R848_Freq_Info_Type
+{
+	u8		RF_POLY;
+	u8		LNA_BAND;
+	u8		LPF_CAP;
+	u8		LPF_NOTCH;
+    u8		XTAL_POW0;
+	u8		CP_CUR;
+	u8		IMR_MEM;
+	u8		Q_CTRL;   
+}R848_Freq_Info_Type;
+
+typedef struct _R848_SysFreq_Info_Type
+{
+	u8		LNA_TOP;
+	u8		LNA_VTH_L;
+	u8		MIXER_TOP;
+	u8		MIXER_VTH_L;
+	u8       RF_TOP;
+	u8       NRB_TOP;
+	u8       NRB_BW;
+	u8       BYP_LPF;
+	u8       RF_FAST_DISCHARGE;
+	u8       RF_SLOW_DISCHARGE;
+	u8       RFPD_PLUSE_ENA;
+	u8       LNA_FAST_DISCHARGE;
+	u8       LNA_SLOW_DISCHARGE;
+	u8       LNAPD_PLUSE_ENA;
+	u8       AGC_CLK;
+
+}R848_SysFreq_Info_Type;
+
+typedef struct _R848_Cal_Info_Type
+{
+	u8		FILTER_6DB;
+	u8		MIXER_AMP_GAIN;
+	u8		MIXER_BUFFER_GAIN;
+	u8		LNA_GAIN;
+	u8		LNA_POWER;
+	u8		RFBUF_OUT;
+	u8		RFBUF_POWER;
+	u8		TF_CAL;
+}R848_Cal_Info_Type;
+
+typedef struct _R848_SectType
+{
+	u8   Phase_Y;
+	u8   Gain_X;
+	u8   Iqcap;
+	u8   Value;
+}R848_SectType;
+
+typedef struct _R848_TF_Result
+{
+	u8   TF_Set;
+	u8   TF_Value;
+}R848_TF_Result;
+
+typedef enum _R848_TF_Band_Type
+{
+    TF_HIGH = 0,
+	TF_MID,
+	TF_LOW
+}R848_TF_Band_Type;
+
+typedef enum _R848_TF_Type
+{
+	R848_TF_NARROW = 0,             //270n/68n   (ISDB-T, DVB-T/T2)
+	R848_TF_BEAD,                   //Bead/68n   (DTMB)
+	R848_TF_NARROW_LIN,             //270n/68n   (N/A)
+	R848_TF_NARROW_ATV_LIN,		//270n/68n   (ATV)
+	R848_TF_BEAD_LIN,               //Bead/68n   (PAL_DK for China Hybrid TV)
+	R848_TF_NARROW_ATSC,		//270n/68n   (ATSC, DVB-C, J83B)
+	R848_TF_BEAD_LIN_ATSC,		//Bead/68n   (ATSC, DVB-C, J83B)
+	R848_TF_82N_BEAD,		//Bead/82n   (DTMB)
+	R848_TF_82N_270N,		//270n/82n   (OTHER Standard)
+	R848_TF_SIZE
+} R848_TF_Type;
+
+
+
+u32 R848_LNA_HIGH_MID[R848_TF_SIZE] = { 644000, 644000, 644000, 644000, 644000, 500000, 500000, 500000, 500000}; 
+u32 R848_LNA_MID_LOW[R848_TF_SIZE] = { 388000, 388000, 348000, 348000, 348000, 300000, 300000, 300000, 300000};
+u32 R848_LNA_LOW_LOWEST[R848_TF_SIZE] = {164000, 164000, 148000, 124000, 124000, 156000, 156000, 108000, 108000};
+
+
+u32 R848_TF_Freq_High[R848_TF_SIZE][R848_TF_HIGH_NUM] = 
+{  	 { 784000, 784000, 776000, 744000, 712000, 680000, 648000, 647000},
+	 { 784000, 784000, 776000, 744000, 712000, 680000, 648000, 647000},
+	 { 784000, 784000, 776000, 744000, 712000, 680000, 648000, 647000},
+	 { 784000, 784000, 776000, 744000, 712000, 680000, 648000, 647000},
+	 { 784000, 784000, 776000, 744000, 712000, 680000, 648000, 647000},
+     { 784000, 784000, 776000, 680000, 608000, 584000, 536000, 504000},
+	 { 784000, 784000, 776000, 680000, 608000, 584000, 536000, 504000},
+	 { 784000, 776000, 712000, 616000, 584000, 560000, 520000, 504000},
+	 { 784000, 776000, 712000, 616000, 584000, 560000, 520000, 504000}
+};
+
+
+u32 R848_TF_Freq_Mid[R848_TF_SIZE][R848_TF_MID_NUM] = 
+{	  {608000, 584000, 560000, 536000, 488000, 440000, 416000, 392000},
+	  {608000, 584000, 560000, 536000, 488000, 440000, 416000, 392000},
+	  {608000, 560000, 536000, 488000, 440000, 392000, 376000, 352000},
+	  {608000, 560000, 536000, 488000, 440000, 392000, 376000, 352000},
+	  {608000, 560000, 536000, 488000, 440000, 392000, 376000, 352000},
+      {488000, 464000, 440000, 416000, 392000, 352000, 320000, 304000},
+	  {488000, 464000, 440000, 416000, 392000, 352000, 320000, 304000},
+	  {480000, 464000, 440000, 416000, 392000, 352000, 320000, 304000},
+	  {480000, 464000, 440000, 416000, 392000, 352000, 320000, 304000},
+};
+u32 R848_TF_Freq_Low[R848_TF_SIZE][R848_TF_LOW_NUM] = 
+{    {320000, 304000, 272000, 240000, 232000, 216000, 192000, 168000},  //164~388
+      {320000, 304000, 272000, 240000, 232000, 216000, 192000, 168000},  //164~388
+	  {256000, 240000, 232000, 224000, 216000, 192000, 168000, 160000},  //148~348
+	  {256000, 240000, 232000, 192000, 160000, 152000, 144000, 128000},  //124~348
+	  {264000, 240000, 192000, 184000, 176000, 152000, 144000, 128000},  //124~348
+      {280000, 248000, 232000, 216000, 192000, 176000, 168000, 160000},  //156~300
+      {280000, 248000, 232000, 216000, 192000, 176000, 168000, 160000},   //156~300
+	  {296000, 280000, 256000, 216000, 184000, 168000, 136000, 112000},   //
+	  {296000, 280000, 256000, 216000, 184000, 168000, 136000, 112000}   //
+};
+u32 R848_TF_Freq_Lowest[R848_TF_SIZE][R848_TF_LOWEST_NUM] = 
+{    {160000, 120000, 104000, 88000, 80000, 72000, 56000, 48000},
+      {160000, 120000, 104000, 88000, 80000, 72000, 56000, 48000},
+	  {144000, 120000, 104000, 88000, 80000, 72000, 56000, 48000},
+	  {120000, 96000,   88000,   80000, 72000, 64000, 56000, 48000},
+	  {104000, 96000,   88000,   80000, 72000, 64000, 56000, 48000},
+	  {136000, 120000, 104000, 88000, 72000, 64000, 56000, 48000},
+	  {128000, 120000, 104000, 96000, 80000, 72000, 64000, 56000},
+	  {104000, 96000, 88000, 80000, 72000, 64000, 56000, 48000},
+	  {104000, 96000, 88000, 80000, 72000, 64000, 56000, 48000}
+};
+
+u8 R848_TF_Result_High[R848_TF_SIZE][R848_TF_HIGH_NUM] = 
+{    {0x00, 0x00, 0x01, 0x03, 0x04, 0x05, 0x07, 0x07},
+      {0x00, 0x00, 0x01, 0x03, 0x04, 0x05, 0x07, 0x07},
+	  {0x00, 0x00, 0x01, 0x03, 0x04, 0x05, 0x07, 0x07},
+	  {0x00, 0x00, 0x01, 0x03, 0x04, 0x05, 0x07, 0x07},
+	  {0x00, 0x00, 0x01, 0x03, 0x04, 0x05, 0x07, 0x07},
+      {0x00, 0x00, 0x01, 0x05, 0x0A, 0x0C, 0x13, 0x19},
+	  {0x00, 0x00, 0x01, 0x05, 0x0A, 0x0C, 0x13, 0x19},
+	  {0x00, 0x03, 0x07, 0x0C, 0x0E, 0x0F, 0x1A, 0x1A},
+	  {0x00, 0x03, 0x07, 0x0C, 0x0E, 0x0F, 0x1A, 0x1A}
+};
+
+u8 R848_TF_Result_Mid[R848_TF_SIZE][R848_TF_MID_NUM] = 
+{    {0x00, 0x01, 0x03, 0x03, 0x06, 0x0B, 0x0E, 0x11},
+      {0x00, 0x01, 0x03, 0x03, 0x06, 0x0B, 0x0E, 0x11},
+	  {0x00, 0x03, 0x03, 0x06, 0x0B, 0x11, 0x12, 0x19},  
+	  {0x00, 0x03, 0x03, 0x06, 0x0B, 0x11, 0x12, 0x19},  
+	  {0x00, 0x03, 0x03, 0x06, 0x0B, 0x11, 0x12, 0x19},
+	  {0x06, 0x08, 0x0B, 0x0E, 0x13, 0x17, 0x1E, 0x1F},
+      {0x06, 0x08, 0x0B, 0x0E, 0x13, 0x17, 0x1E, 0x1F},
+	  {0x09, 0x0D, 0x10, 0x12, 0x16, 0x1B, 0x1E, 0x1F},
+	  {0x09, 0x0D, 0x10, 0x12, 0x16, 0x1B, 0x1E, 0x1F}
+};
+u8 R848_TF_Result_Low[R848_TF_SIZE][R848_TF_LOW_NUM] = 
+{    {0x00, 0x02, 0x04, 0x07, 0x0A, 0x0B, 0x0F, 0x16},
+      {0x00, 0x02, 0x04, 0x07, 0x0A, 0x0B, 0x0F, 0x16},
+	  {0x05, 0x07, 0x0A, 0x0B, 0x0B, 0x0F, 0x16, 0x1A},
+	  {0x05, 0x07, 0x0A, 0x0F, 0x1A, 0x1A, 0x23, 0x2A},
+	  {0x05, 0x08, 0x10, 0x13, 0x1A, 0x1A, 0x23, 0x2A},
+	  {0x05, 0x08, 0x0C, 0x0E, 0x10, 0x14, 0x18, 0x1A},
+	  {0x05, 0x08, 0x0C, 0x0E, 0x10, 0x14, 0x18, 0x1A},
+	  {0x00, 0x01, 0x03, 0x07, 0x0D, 0x11, 0x1E, 0x2F},
+	  {0x00, 0x01, 0x03, 0x07, 0x0D, 0x11, 0x1E, 0x2F}
+};
+u8 R848_TF_Result_Lowest[R848_TF_SIZE][R848_TF_LOWEST_NUM] = 
+{    {0x00, 0x06, 0x0C, 0x15, 0x1C, 0x1F, 0x3C, 0x3F},
+      {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08},
+	  {0x02, 0x06, 0x0C, 0x15, 0x1C, 0x1F, 0x3C, 0x3F},
+	  {0x06, 0x11, 0x15, 0x1C, 0x1F, 0x2F, 0x3C, 0x3F},
+      {0x04, 0x08, 0x08, 0x08, 0x10, 0x12, 0x13, 0x13},
+	  {0x06, 0x09, 0x0E, 0x18, 0x25, 0x2F, 0x3C, 0x3F},
+	  {0x00, 0x04, 0x04, 0x08, 0x08, 0x10, 0x12, 0x13},
+	  {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08},
+	  {0x0E, 0x14, 0x18, 0x1E, 0x25, 0x2F, 0x3C, 0x3F}
+};
+
+
+u8 R848_iniArray_hybrid[R848_REG_NUM] = {
+						0x00, 0x00, 0x40, 0x44, 0x17, 0x00, 0x06, 0xF0, 0x00, 0x41,
+					//  0x08  0x09  0x0A  0x0B  0x0C  0x0D  0x0E  0x0F  0x10  0x11
+						0x7B, 0x0B, 0x70, 0x06, 0x6E, 0x20, 0x70, 0x87, 0x96, 0x00,
+					//  0x12  0x13  0x14  0x15  0x16  0x17  0x18  0x19  0x1A  0x1B  
+						0x10, 0x00, 0x80, 0xA5, 0xB7, 0x00, 0x40, 0xCB, 0x95, 0xF0,
+					//  0x1C  0x1D  0x1E  0x1F  0x20  0x21  0x22  0x23  0x24  0x25
+						0x24, 0x00, 0xFD, 0x8B, 0x17, 0x13, 0x01, 0x07, 0x01, 0x3F};
+					//  0x26  0x27  0x28  0x29  0x2A  0x2B  0x2C  0x2D  0x2E  0x2F
+
+
+
+u8 R848_iniArray_dvbs[R848_REG_NUM] = {
+						0x80, 0x05, 0x40, 0x40, 0x1F, 0x1F, 0x07, 0xFF, 0x00, 0x40,
+					//  0x08  0x09  0x0A  0x0B  0x0C  0x0D  0x0E  0x0F  0x10  0x11
+						0xF0, 0x0F, 0x4D, 0x06, 0x6F, 0x20, 0x28, 0x83, 0x96, 0x00,  //0x16[1] pulse_flag HPF : Bypass ;  0x19[1:0] Deglich SW Cur : highest
+					//  0x12  0x13  0x14  0x15  0x16  0x17  0x18  0x19  0x1A  0x1B   
+						0x1C, 0x99, 0xC1, 0x83, 0xB7, 0x00, 0x4F, 0xCB, 0x95, 0xFD,
+					//  0x1C  0x1D  0x1E  0x1F  0x20  0x21  0x22  0x23  0x24  0x25
+						0xA4, 0x01, 0x24, 0x0B, 0x4F, 0x05, 0x01, 0x47, 0x3F, 0x3F};
+					//  0x26  0x27  0x28  0x29  0x2A  0x2B  0x2C  0x2D  0x2E  0x2F
+
+R848_SectType R848_IMR_Data[5] = {
+									{0, 0, 0, 0},
+									{0, 0, 0, 0},
+									{0, 0, 0, 0},
+									{0, 0, 0, 0},
+									{0, 0, 0, 0}
+									};//Please keep this array data for standby mode.
+
+
+
+
+
+
+typedef enum _R848_UL_TF_Type
+{
+	R848_UL_USING_BEAD = 0,            
+    R848_UL_USING_270NH,                      
+}R848_UL_TF_Type;
+
+
+
+typedef enum _R848_Cal_Type
+{
+	R848_IMR_CAL = 0,
+	R848_IMR_LNA_CAL,
+	R848_TF_CAL,
+	R848_TF_LNA_CAL,
+	R848_LPF_CAL,
+	R848_LPF_LNA_CAL
+}R848_Cal_Type;
+
+typedef enum _R848_BW_Type
+{
+	BW_6M = 0,
+	BW_7M,
+	BW_8M,
+	BW_1_7M,
+	BW_10M,
+	BW_200K
+}R848_BW_Type;
+
+
+enum R848_XTAL_PWR_VALUE
+{
+	XTAL_SMALL_LOWEST = 0,
+    XTAL_SMALL_LOW,
+    XTAL_SMALL_HIGH,
+    XTAL_SMALL_HIGHEST,
+    XTAL_LARGE_HIGHEST,
+	XTAL_CHECK_SIZE
+};
+
+
+typedef enum _R848_Xtal_Div_TYPE
+{
+	XTAL_DIV1 = 0,
+	XTAL_DIV2
+}R848_Xtal_Div_TYPE;
+
+
+//----------------------------------------------------------//
+//                   R848 Public Parameter                     //
+//----------------------------------------------------------//
+typedef enum _R848_ErrCode
+{
+	RT_Success = 0,
+	RT_Fail    = 1
+}R848_ErrCode;
+
+typedef enum _R848_Standard_Type  //Don't remove standand list!!
+{
+	R848_DVB_T_6M = 0,
+	R848_DVB_T_7M,
+	R848_DVB_T_8M, 
+    R848_DVB_T2_6M,			//IF=4.57M
+	R848_DVB_T2_7M,			//IF=4.57M
+	R848_DVB_T2_8M,			//IF=4.57M
+	R848_DVB_T2_1_7M,
+	R848_DVB_T2_10M,
+	R848_DVB_C_8M,
+	R848_DVB_C_6M, 
+	R848_J83B,
+	R848_ISDB_T,             //IF=4.063M
+	R848_ISDB_T_4570,		 //IF=4.57M
+	R848_DTMB_4570,			 //IF=4.57M
+	R848_DTMB_6000,			 //IF=6.00M
+	R848_DTMB_6M_BW_IF_5M,   //IF=5.0M, BW=6M
+	R848_DTMB_6M_BW_IF_4500, //IF=4.5M, BW=6M
+	R848_ATSC,
+	R848_DVB_S,
+	R848_DVB_T_6M_IF_5M,
+	R848_DVB_T_7M_IF_5M,
+	R848_DVB_T_8M_IF_5M,
+	R848_DVB_T2_6M_IF_5M,
+	R848_DVB_T2_7M_IF_5M,
+	R848_DVB_T2_8M_IF_5M,
+	R848_DVB_T2_1_7M_IF_5M,
+	R848_DVB_C_8M_IF_5M,
+	R848_DVB_C_6M_IF_5M, 
+	R848_J83B_IF_5M,
+	R848_ISDB_T_IF_5M,            
+	R848_DTMB_IF_5M,     
+	R848_ATSC_IF_5M,
+	R848_FM,
+	R848_STD_SIZE,
+}R848_Standard_Type;
+
+typedef enum _R848_GPO_Type
+{
+	HI_SIG = 0,
+	LO_SIG = 1
+}R848_GPO_Type;
+
+typedef enum _R848_RF_Gain_TYPE
+{
+	RF_AUTO = 0,
+	RF_MANUAL
+}R848_RF_Gain_TYPE;
+
+typedef enum _R848_DVBS_OutputSignal_Type
+{
+	DIFFERENTIALOUT = 0,
+	SINGLEOUT     = 1
+}R848_DVBS_OutputSignal_Type;
+
+typedef enum _R848_DVBS_AGC_Type
+{
+	AGC_NEGATIVE = 0,
+	AGC_POSITIVE = 1
+}R848_DVBS_AGC_Type;
+
+
+
+typedef struct _R848_Set_Info
+{
+	u32                       RF_KHz;
+	u32						 DVBS_BW;
+	R848_Standard_Type           R848_Standard;
+	R848_DVBS_OutputSignal_Type  R848_DVBS_OutputSignal_Mode;
+	R848_DVBS_AGC_Type           R848_DVBS_AGC_Mode; 
+}R848_Set_Info;
+
+typedef struct _R848_RF_Gain_Info
+{
+	u16   RF_gain_comb;
+	u8   RF_gain1;
+	u8   RF_gain2;
+	u8   RF_gain3;
+}R848_RF_Gain_Info;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#endif /* R848_PRIV_H */
diff -rpuN a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
--- a/drivers/media/dvb/dvb-usb/Kconfig	2016-04-09 10:44:38.096009429 -0300
+++ b/drivers/media/dvb/dvb-usb/Kconfig	2016-04-09 10:34:50.364008344 -0300
@@ -429,3 +429,12 @@ config DVB_USB_RTL2832U
 	default m
 	help
 	  Say Y or M to support the Realtek RTL2832 / R820T DVB-T receiver
+
+config DVB_USB_TBS5520
+	tristate "Turbosight TBS5520 support"
+	depends on DVB_USB
+	select DVB_AVL6882 if !MEDIA_TUNER_CUSTOMISE
+	select MEDIA_TUNER_R848 if !MEDIA_TUNER_CUSTOMISE
+	help
+	  Say Y here to support the Turbosight TBS5520 USB2 DVB-T/T2/C/S/S2 device
+
diff -rpuN a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile
--- a/drivers/media/dvb/dvb-usb/Makefile	2016-04-09 10:44:38.100009433 -0300
+++ b/drivers/media/dvb/dvb-usb/Makefile	2016-04-09 10:40:31.492008966 -0300
@@ -122,6 +122,10 @@ dvb-usb-rtl2832u-objs := demod_rtl2832.o
                         nim_rtl2832_fc0013.o tuner_fc0013.o rtl2832u_audio.o tuner_r820t.o nim_rtl2832_r820t.o
 obj-$(CONFIG_DVB_USB_RTL2832U) += dvb-usb-rtl2832u.o
 
+# DVB-T/T2/C/S/S2 (TBS5520)
+dvb-usb-tbs5520-objs := tbs5520.o
+obj-$(CONFIG_DVB_USB_TBS5520) += dvb-usb-tbs5520.o
+
 ccflags-y += -I$(srctree)/drivers/media/dvb/dvb-core
 ccflags-y += -I$(srctree)/drivers/media/dvb/frontends/
 # due to tuner-xc3028
diff -rpuN a/drivers/media/dvb/dvb-usb/tbs5520.c b/drivers/media/dvb/dvb-usb/tbs5520.c
--- a/drivers/media/dvb/dvb-usb/tbs5520.c	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/dvb-usb/tbs5520.c	2016-04-09 10:31:21.252007846 -0300
@@ -0,0 +1,464 @@
+/*
+ * TurboSight TBS 5520  driver
+ *
+ * Copyright (c) 2013 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation, version 2.
+ *
+ */
+
+#include <linux/version.h>
+#include "tbs5520.h"
+
+#include "avl6882.h"
+#include "r848.h"
+
+#ifndef USB_PID_tbs5520
+#define USB_PID_tbs5520 0x5520
+#endif
+
+#define tbs5520_READ_MSG 0
+#define tbs5520_WRITE_MSG 1
+
+#define tbs5520_RC_QUERY (0x1a00)
+
+struct tbs5520_state {
+	u32 last_key_pressed;
+};
+
+/* debug */
+static int dvb_usb_tbs5520_debug;
+module_param_named(debug, dvb_usb_tbs5520_debug, int, 0644);
+MODULE_PARM_DESC(debug, "set debugging level (1=info 2=xfer (or-able))." 
+							DVB_USB_DEBUG_STATUS);
+
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+static int tbs5520_op_rw(struct usb_device *dev, u8 request, u16 value,
+				u16 index, u8 * data, u16 len, int flags)
+{
+	int ret;
+	u8 u8buf[len];
+
+	unsigned int pipe = (flags == tbs5520_READ_MSG) ?
+			usb_rcvctrlpipe(dev, 0) : usb_sndctrlpipe(dev, 0);
+	u8 request_type = (flags == tbs5520_READ_MSG) ? USB_DIR_IN : 
+								USB_DIR_OUT;
+
+	if (flags == tbs5520_WRITE_MSG)
+		memcpy(u8buf, data, len);
+	ret = usb_control_msg(dev, pipe, request, request_type | 
+			USB_TYPE_VENDOR, value, index , u8buf, len, 2000);
+
+	if (flags == tbs5520_READ_MSG)
+		memcpy(data, u8buf, len);
+	return ret;
+}
+
+/* I2C */
+static int tbs5520_i2c_transfer(struct i2c_adapter *adap, 
+					struct i2c_msg msg[], int num)
+{
+	struct dvb_usb_device *d = i2c_get_adapdata(adap);
+	int i = 0;
+	u8 buf6[100];
+	u8 inbuf[100];
+
+
+
+	if (!d)
+	{
+		return -ENODEV;
+	}
+	if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
+	{
+		return -EAGAIN;
+	}
+	switch (num) {
+	case 2:
+		buf6[0]=msg[1].len;//lenth
+		buf6[1]=(msg[0].addr<<1)+1;//demod addr
+
+		//register
+		//buf6[2] = 0;
+		tbs5520_op_rw(d->udev, 0x93, 0, 0,
+					buf6, 2, tbs5520_WRITE_MSG);
+		//msleep(5);
+		tbs5520_op_rw(d->udev, 0x91, 0, 0,
+					inbuf, buf6[0], tbs5520_READ_MSG);
+		memcpy(msg[1].buf, inbuf, msg[1].len);
+
+		break;
+	case 1:
+		switch (msg[0].addr) {
+		case 0x14:
+		case 0x7a:
+			if (msg[0].flags == 0) {
+				buf6[0] = msg[0].len+1;//lenth
+				buf6[1] = msg[0].addr<<1;//addr
+				for(i=0;i<msg[0].len;i++) {
+					buf6[2+i] = msg[0].buf[i];//register
+				}
+				tbs5520_op_rw(d->udev, 0x80, 0, 0,
+					buf6, msg[0].len+2, tbs5520_WRITE_MSG);
+			} else {
+				tbs5520_op_rw(d->udev, 0x82, 0, 0,
+					msg[0].buf, 64, tbs5520_WRITE_MSG);
+
+			}
+
+			//msleep(3);
+			break;
+			
+		case (tbs5520_RC_QUERY):
+			tbs5520_op_rw(d->udev, 0xb8, 0, 0,
+					buf6, 4, tbs5520_READ_MSG);
+			msg[0].buf[0] = buf6[2];
+			msg[0].buf[1] = buf6[3];
+			//msleep(3);
+			//info("tbs5520_RC_QUERY %x %x %x %x\n",
+			//		buf6[0],buf6[1],buf6[2],buf6[3]);
+			break;
+		}
+
+		break;
+	}
+
+	mutex_unlock(&d->i2c_mutex);
+	return num;
+}
+
+static u32 tbs5520_i2c_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_I2C;
+}
+
+static struct r848_config r848_config = {
+	.i2c_address = 0x7a,
+
+	.R848_DetectTfType = 0, //R848_UL_USING_BEAD,
+	.R848_pre_standard = 33, //R848_STD_SIZE,
+	.R848_Xtal_Pwr = 3, //XTAL_SMALL_HIGHEST,
+	.R848_Xtal_Pwr_tmp = 4, //XTAL_LARGE_HIGHEST,
+
+	/* dvb t/c */
+	.R848_SetTfType = 1, //R848_TF_BEAD,
+};
+
+
+static struct avl6882_config avl6882_config = {
+	.demod_address = 0x14,
+	.tuner_address = 0x7A,
+	.eDiseqcStatus = 0, //AVL_DOS_Uninitialized,
+
+};
+
+static struct i2c_algorithm tbs5520_i2c_algo = {
+	.master_xfer = tbs5520_i2c_transfer,
+	.functionality = tbs5520_i2c_func,
+};
+
+static int tbs5520_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
+{
+
+	int i,ret;
+
+
+	u8 ibuf[3] = {0, 0,0};
+	u8 eeprom[256], eepromline[16];
+
+return 0;
+
+	for (i = 0; i < 256; i++) {
+		ibuf[0]=1;//lenth
+		ibuf[1]=0xa0;//eeprom addr
+		ibuf[2]=i;//register
+		ret = tbs5520_op_rw(d->udev, 0x90, 0, 0,
+					ibuf, 3, tbs5520_WRITE_MSG);
+		ret = tbs5520_op_rw(d->udev, 0x91, 0, 0,
+					ibuf, 1, tbs5520_READ_MSG);
+			if (ret < 0) {
+				err("read eeprom failed.");
+				return -1;
+			} else {
+				eepromline[i%16] = ibuf[0];
+				eeprom[i] = ibuf[0];
+			}
+			
+			if ((i % 16) == 15) {
+				deb_xfer("%02x: ", i - 15);
+				debug_dump(eepromline, 16, deb_xfer);
+			}
+	}
+	memcpy(mac, eeprom + 16, 6);
+	return 0;
+};
+
+static struct dvb_usb_device_properties tbs5520_properties;
+
+static int tbs5520_frontend_attach(struct dvb_usb_adapter *d)
+{
+	u8 buf[20];
+
+	d->fe_adap->fe = dvb_attach(avl6882_attach, &avl6882_config,
+		&d->dev->i2c_adap);
+	if (d->fe_adap->fe == NULL)
+		goto err;
+
+	if (dvb_attach(r848_attach, d->fe_adap->fe, &r848_config,
+			&d->dev->i2c_adap) == NULL) {
+			//tas2101_get_i2c_adapter(d->fe_adap->fe, 2)) == NULL) {
+		dvb_frontend_detach(d->fe_adap->fe);
+		d->fe_adap->fe = NULL;
+		printk("TBS5520: tuner attach failed\n");
+		goto err;
+	}
+
+	info("TBS5520: frontend attached\n");
+	buf[0] = 7;
+	buf[1] = 1;
+	tbs5520_op_rw(d->dev->udev, 0x8a, 0, 0,
+		buf, 2, tbs5520_WRITE_MSG);
+
+	buf[0] = 6;
+	buf[1] = 1;
+	tbs5520_op_rw(d->dev->udev, 0x8a, 0, 0,
+		buf, 2, tbs5520_WRITE_MSG);
+
+
+	return 0;
+err:
+	printk("TBS5520: frontend attach failed\n");
+	return -ENODEV;
+}
+
+static struct rc_map_table tbs5520_rc_keys[] = {
+	{ 0xff84, KEY_POWER2},		/* power */
+	{ 0xff94, KEY_MUTE},		/* mute */
+	{ 0xff87, KEY_1},
+	{ 0xff86, KEY_2},
+	{ 0xff85, KEY_3},
+	{ 0xff8b, KEY_4},
+	{ 0xff8a, KEY_5},
+	{ 0xff89, KEY_6},
+	{ 0xff8f, KEY_7},
+	{ 0xff8e, KEY_8},
+	{ 0xff8d, KEY_9},
+	{ 0xff92, KEY_0},
+	{ 0xff96, KEY_CHANNELUP},	/* ch+ */
+	{ 0xff91, KEY_CHANNELDOWN},	/* ch- */
+	{ 0xff93, KEY_VOLUMEUP},	/* vol+ */
+	{ 0xff8c, KEY_VOLUMEDOWN},	/* vol- */
+	{ 0xff83, KEY_RECORD},		/* rec */
+	{ 0xff98, KEY_PAUSE},		/* pause, yellow */
+	{ 0xff99, KEY_OK},		/* ok */
+	{ 0xff9a, KEY_CAMERA},		/* snapshot */
+	{ 0xff81, KEY_UP},
+	{ 0xff90, KEY_LEFT},
+	{ 0xff82, KEY_RIGHT},
+	{ 0xff88, KEY_DOWN},
+	{ 0xff95, KEY_FAVORITES},	/* blue */
+	{ 0xff97, KEY_SUBTITLE},	/* green */
+	{ 0xff9d, KEY_ZOOM},
+	{ 0xff9f, KEY_EXIT},
+	{ 0xff9e, KEY_MENU},
+	{ 0xff9c, KEY_EPG},
+	{ 0xff80, KEY_PREVIOUS},	/* red */
+	{ 0xff9b, KEY_MODE},
+	{ 0xffdd, KEY_TV },
+	{ 0xffde, KEY_PLAY },
+	{ 0xffdc, KEY_STOP },
+	{ 0xffdb, KEY_REWIND },
+	{ 0xffda, KEY_FASTFORWARD },
+	{ 0xffd9, KEY_PREVIOUS },	/* replay */
+	{ 0xffd8, KEY_NEXT },		/* skip */
+	{ 0xffd1, KEY_NUMERIC_STAR },
+	{ 0xffd2, KEY_NUMERIC_POUND },
+	{ 0xffd4, KEY_DELETE },		/* clear */
+};
+
+static int tbs5520_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
+{
+	struct rc_map_table *keymap = d->props.rc.legacy.rc_map_table;
+	int keymap_size = d->props.rc.legacy.rc_map_size;
+
+	struct tbs5520_state *st = d->priv;
+	u8 key[2];
+	struct i2c_msg msg[] = {
+		{.addr = tbs5520_RC_QUERY, .flags = I2C_M_RD, .buf = key,
+		.len = 2},
+	};
+	int i;
+
+	*state = REMOTE_NO_KEY_PRESSED;
+	if (tbs5520_i2c_transfer(&d->i2c_adap, msg, 1) == 1) {
+		//info("key: %x %x\n",msg[0].buf[0],msg[0].buf[1]); 
+		for (i = 0; i < keymap_size; i++) {
+			if (rc5_data(&keymap[i]) == msg[0].buf[1]) {
+				*state = REMOTE_KEY_PRESSED;
+				*event = keymap[i].keycode;
+				st->last_key_pressed =
+					keymap[i].keycode;
+				break;
+			}
+		st->last_key_pressed = 0;
+		}
+	}
+	 
+	return 0;
+}
+
+static struct usb_device_id tbs5520_table[] = {
+	{USB_DEVICE(0x734c, 0x5520)},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(usb, tbs5520_table);
+
+static int tbs5520_load_firmware(struct usb_device *dev,
+			const struct firmware *frmwr)
+{
+	u8 *b, *p;
+	int ret = 0, i;
+	u8 reset;
+	const struct firmware *fw;
+	const char *filename = "dvb-usb-tbs5520.fw";
+	switch (dev->descriptor.idProduct) {
+	case 0xdc02:
+		ret = request_firmware(&fw, filename, &dev->dev);
+		if (ret != 0) {
+			err("did not find the firmware file. (%s) "
+			"Please see linux/Documentation/dvb/ for more details "
+			"on firmware-problems.", filename);
+			return ret;
+		}
+		break;
+	default:
+		fw = frmwr;
+		break;
+	}
+	info("start downloading tbs5520 firmware");
+	p = kmalloc(fw->size, GFP_KERNEL);
+	reset = 1;
+	/*stop the CPU*/
+	tbs5520_op_rw(dev, 0xa0, 0x7f92, 0, &reset, 1, tbs5520_WRITE_MSG);
+	tbs5520_op_rw(dev, 0xa0, 0xe600, 0, &reset, 1, tbs5520_WRITE_MSG);
+
+	if (p != NULL) {
+		memcpy(p, fw->data, fw->size);
+		for (i = 0; i < fw->size; i += 0x40) {
+			b = (u8 *) p + i;
+			if (tbs5520_op_rw(dev, 0xa0, i, 0, b , 0x40,
+					tbs5520_WRITE_MSG) != 0x40) {
+				err("error while transferring firmware");
+				ret = -EINVAL;
+				break;
+			}
+		}
+		/* restart the CPU */
+		reset = 0;
+		if (ret |= tbs5520_op_rw(dev, 0xa0, 0x7f92, 0, &reset, 1,
+					tbs5520_WRITE_MSG) != 1) {
+			err("could not restart the USB controller CPU.");
+			ret = -EINVAL;
+		}
+		if (ret |= tbs5520_op_rw(dev, 0xa0, 0xe600, 0, &reset, 1,
+					tbs5520_WRITE_MSG) != 1) {
+			err("could not restart the USB controller CPU.");
+			ret = -EINVAL;
+		}
+
+		msleep(100);
+		kfree(p);
+	}
+	info("end downloading tbs5520 firmware");
+	return ret;
+}
+
+static struct dvb_usb_device_properties tbs5520_properties = {
+	.caps = DVB_USB_IS_AN_I2C_ADAPTER,
+	.usb_ctrl = DEVICE_SPECIFIC,
+	.firmware = "dvb-usb-tbs5520.fw",
+	.size_of_priv = sizeof(struct tbs5520_state),
+	.no_reconnect = 1,
+
+	.i2c_algo = &tbs5520_i2c_algo,
+	.rc.legacy = {
+		.rc_map_table = tbs5520_rc_keys,
+		.rc_map_size = ARRAY_SIZE(tbs5520_rc_keys),
+		.rc_interval = 150,
+		.rc_query = tbs5520_rc_query,
+	},
+
+	.generic_bulk_ctrl_endpoint = 0x81,
+	/* parameter for the MPEG2-data transfer */
+	.num_adapters = 1,
+	.download_firmware = tbs5520_load_firmware,
+	.read_mac_address = tbs5520_read_mac_address,
+	.adapter = {{
+		.num_frontends = 1,
+		.fe = {{
+			.frontend_attach = tbs5520_frontend_attach,
+			.streaming_ctrl = NULL,
+			.tuner_attach = NULL,
+			.stream = {
+				.type = USB_BULK,
+				.count = 8,
+				.endpoint = 0x82,
+				.u = {
+					.bulk = {
+						.buffersize = 4096,
+					}
+				}
+			},
+		}},
+	}},
+	.num_device_descs = 1,
+	.devices = {
+		{"TBS 5520 USB2.0",
+			{&tbs5520_table[0], NULL},
+			{NULL},
+		}
+	}
+};
+
+static int tbs5520_probe(struct usb_interface *intf,
+		const struct usb_device_id *id)
+{
+	if (0 == dvb_usb_device_init(intf, &tbs5520_properties,
+			THIS_MODULE, NULL, adapter_nr)) {
+		return 0;
+	}
+	return -ENODEV;
+}
+
+static struct usb_driver tbs5520_driver = {
+	.name = "tbs5520",
+	.probe = tbs5520_probe,
+	.disconnect = dvb_usb_device_exit,
+	.id_table = tbs5520_table,
+};
+
+static int __init tbs5520_module_init(void)
+{
+	int ret =  usb_register(&tbs5520_driver);
+	if (ret)
+		err("usb_register failed. Error number %d", ret);
+
+	return ret;
+}
+
+static void __exit tbs5520_module_exit(void)
+{
+	usb_deregister(&tbs5520_driver);
+}
+
+module_init(tbs5520_module_init);
+module_exit(tbs5520_module_exit);
+
+MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
+MODULE_DESCRIPTION("TurboSight TBS 5520 driver");
+MODULE_VERSION("1.0");
+MODULE_LICENSE("GPL");
diff -rpuN a/drivers/media/dvb/dvb-usb/tbs5520.h b/drivers/media/dvb/dvb-usb/tbs5520.h
--- a/drivers/media/dvb/dvb-usb/tbs5520.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/dvb-usb/tbs5520.h	2016-04-09 10:31:21.252007846 -0300
@@ -0,0 +1,8 @@
+#ifndef _TBS5520_H_
+#define _TBS5520_H_
+
+#define DVB_USB_LOG_PREFIX "tbs5520"
+#include "dvb-usb.h"
+
+#define deb_xfer(args...) dprintk(dvb_usb_tbs5520_debug, 0x02, args)
+#endif
diff -rpuN a/drivers/media/dvb/frontends/avl6882.c b/drivers/media/dvb/frontends/avl6882.c
--- a/drivers/media/dvb/frontends/avl6882.c	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/frontends/avl6882.c	2016-04-09 10:31:21.244008001 -0300
@@ -0,0 +1,2488 @@
+/*
+ * Availink AVL6882 demod driver
+ *
+ * Copyright (C) 2015 Luis Alves <ljalvs@gmail.com>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License along
+ *    with this program; if not, write to the Free Software Foundation, Inc.,
+ *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/bitrev.h>
+
+#include "dvb_frontend.h"
+#include "avl6882.h"
+#include "avl6882_priv.h"
+
+#include "AVL_Demod_Patch_DVBSxFw_.h"
+#include "AVL_Demod_Patch_DVBCFw_.h"
+#include "AVL_Demod_Patch_DVBTxFw_.h"
+
+
+static int avl6882_i2c_rd(struct avl6882_priv *priv, u8 *buf, int len)
+{
+	int ret;
+	struct i2c_msg msg[] = {
+		{
+			.addr = priv->config->demod_address,
+			.flags = 0,
+			.len = 1,
+			.buf = 0,
+		},
+		{
+			.addr= priv->config->demod_address,
+			.flags= I2C_M_RD,
+			.len  = len,
+			.buf  = buf,
+		}
+	};
+
+	ret = i2c_transfer(priv->i2c, msg, 2);
+	if (ret == 2) {
+		ret = 0;
+	} else {
+		dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d " \
+				"len=%d\n", KBUILD_MODNAME, ret, len);
+		ret = -EREMOTEIO;
+	}
+	return ret;
+}
+
+
+static int avl6882_i2c_wr(struct avl6882_priv *priv, u8 *buf, int len)
+{
+	int ret;
+	struct i2c_msg msg = {
+		.addr= priv->config->demod_address,
+		.flags = 0,
+		.buf = buf,
+		.len = len,
+	};
+
+	ret = i2c_transfer(priv->i2c, &msg, 1);
+	if (ret == 1) {
+		ret = 0;
+	} else {
+		dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d " \
+				"len=%d\n", KBUILD_MODNAME, ret, len);
+		ret = -EREMOTEIO;
+	}
+	return ret;
+}
+
+
+static int avl6882_i2c_wrm(struct avl6882_priv *priv, u8 *buf, int len)
+{
+	int ret;
+	struct i2c_msg msg = {
+		.addr= priv->config->demod_address,
+		.flags = 1, /* ?? */
+		.buf = buf,
+		.len = len,
+	};
+
+	ret = i2c_transfer(priv->i2c, &msg, 1);
+	if (ret == 1) {
+		ret = 0;
+	} else {
+		dev_warn(&priv->i2c->dev, "%s: i2c wrm failed=%d " \
+				"len=%d\n", KBUILD_MODNAME, ret, len);
+		ret = -EREMOTEIO;
+	}
+	return ret;
+}
+
+
+/* write 32bit words at addr */
+#define MAX_WORDS_WR_LEN	((MAX_II2C_WRITE_SIZE-3) / 4)
+static int avl6882_i2c_wr_data(struct avl6882_priv *priv,
+	u32 addr, u32 *data, int len)
+{
+	int ret = 0, this_len;
+	u8 buf[MAX_II2C_WRITE_SIZE];
+	u8 *p;
+
+	while (len > 0) {
+		p = buf;
+		*(p++) = (u8) (addr >> 16);
+		*(p++) = (u8) (addr >> 8);
+		*(p++) = (u8) (addr);
+
+		this_len = (len > MAX_WORDS_WR_LEN) ? MAX_WORDS_WR_LEN : len;
+		len -= this_len;
+		if (len)
+			addr += this_len * 4;
+
+		while (this_len--) {
+			*(p++) = (u8) ((*data) >> 24);
+			*(p++) = (u8) ((*data) >> 16);
+			*(p++) = (u8) ((*data) >> 8);
+			*(p++) = (u8) (*(data++));
+		}
+
+		if (len > 0)
+			ret = avl6882_i2c_wrm(priv, buf, (int) (p - buf));
+		else
+			ret = avl6882_i2c_wr(priv, buf, (int) (p - buf));
+		if (ret)
+			break;
+	}
+	return ret;
+}
+
+static int avl6882_i2c_wr_reg(struct avl6882_priv *priv,
+	u32 addr, u32 data, int reg_size)
+{
+	u8 buf[3 + 4];
+	u8 *p = buf;
+
+	*(p++) = (u8) (addr >> 16);
+	*(p++) = (u8) (addr >> 8);
+	*(p++) = (u8) (addr);
+
+	switch (reg_size) {
+	case 4:
+		*(p++) = (u8) (data >> 24);
+		*(p++) = (u8) (data >> 16);
+	case 2:
+		*(p++) = (u8) (data >> 8);
+	case 1:
+	default:
+		*(p++) = (u8) (data);
+		break;
+	}
+
+	return avl6882_i2c_wr(priv, buf, 3 + reg_size);
+}
+
+#define AVL6882_WR_REG8(_priv, _addr, _data) \
+	avl6882_i2c_wr_reg(_priv, _addr, _data, 1)
+#define AVL6882_WR_REG16(_priv, _addr, _data) \
+	avl6882_i2c_wr_reg(_priv, _addr, _data, 2)
+#define AVL6882_WR_REG32(_priv, _addr, _data) \
+	avl6882_i2c_wr_reg(_priv, _addr, _data, 4)
+
+
+static int avl6882_i2c_rd_reg(struct avl6882_priv *priv,
+	u32 addr, u32 *data, int reg_size)
+{
+	int ret;
+	u8 buf[3 + 4];
+	u8 *p = buf;
+
+	*(p++) = (u8) (addr >> 16);
+	*(p++) = (u8) (addr >> 8);
+	*(p++) = (u8) (addr);
+	ret = avl6882_i2c_wr(priv, buf, 3);
+	ret |= avl6882_i2c_rd(priv, buf, reg_size);
+
+	*data = 0;
+	p = buf;
+
+	switch (reg_size) {
+	case 4:
+		*data |= (u32) (*(p++)) << 24;
+		*data |= (u32) (*(p++)) << 16;
+	case 2:
+		*data |= (u32) (*(p++)) << 8;
+	case 1:
+	default:
+		*data |= (u32) *(p);
+		break;
+	}
+	return ret;
+}
+
+#define AVL6882_RD_REG8(_priv, _addr, _data) \
+	avl6882_i2c_rd_reg(_priv, _addr, _data, 1)
+#define AVL6882_RD_REG16(_priv, _addr, _data) \
+	avl6882_i2c_rd_reg(_priv, _addr, _data, 2)
+#define AVL6882_RD_REG32(_priv, _addr, _data) \
+	avl6882_i2c_rd_reg(_priv, _addr, _data, 4)
+
+
+static int avl6882_setup_pll(struct avl6882_priv *priv)
+{
+	int ret;
+
+	// sys_pll
+	ret = AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_divr, 2);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_divf, 99);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_divq, 7);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_range, 1);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_divq2, 11);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_divq3, 13);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_enable2, 0);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_sys_pll_enable3, 0);
+
+	//mpeg_pll
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_divr, 0);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_divf, 35);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_divq, 7);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_range, 3);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_divq2, 11);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_divq3, 13);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_enable2, 0);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_mpeg_pll_enable3, 0);
+
+	//adc_pll
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_divr, 2);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_divf, 99);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_divq, 7);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_range, 1);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_divq2, 11);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_divq3, 13);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_enable2, 1);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_adc_pll_enable3, 1);
+
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_reset_register, 0);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_reset_register, 1);
+	msleep(20);
+
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_dll_out_phase, 96);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_dll_rd_phase, 0);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_deglitch_mode, 1);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_dll_init, 1);
+	ret |= AVL6882_WR_REG32(priv, hw_E2_AVLEM61_dll_init, 0);
+	return ret;
+}
+
+
+#define DEMOD_WAIT_RETRIES	(10)
+#define DEMOD_WAIT_MS		(20)
+static int avl6882_wait_demod(struct avl6882_priv *priv)
+{
+	u32 cmd = 0;
+	int ret, retry = DEMOD_WAIT_RETRIES;
+
+	do {
+		ret = AVL6882_RD_REG16(priv,0x200 + rc_fw_command_saddr_offset, &cmd);
+		if ((ret == 0) && (cmd == 0))
+			return ret;
+		else
+			msleep(DEMOD_WAIT_MS);
+	} while (--retry);
+	ret = -EBUSY;
+	return ret;
+}
+
+/* TODO remove one of the waits */
+static int avl6882_exec_n_wait(struct avl6882_priv *priv, u8 cmd)
+{
+	int ret;
+
+	ret = avl6882_wait_demod(priv);
+	if (ret)
+		return ret;
+	ret = AVL6882_WR_REG16(priv, 0x200 + rc_fw_command_saddr_offset, (u32) cmd);
+	if (ret)
+		return ret;
+	return avl6882_wait_demod(priv);
+}
+
+
+#define DMA_MAX_TRIES	(20)
+static int avl6882_patch_demod(struct avl6882_priv *priv, u32 *patch)
+{
+	int ret = 0;
+	u8 unary_op, binary_op, addr_mode_op;
+	u32 cmd, num_cmd_words, next_cmd_idx, num_cond_words, num_rvs;
+	u32 condition = 0;
+	u32 value = 0;
+	u32 operation;
+	u32 tmp_top_valid, core_rdy_word;
+	u32 exp_crc_val, crc_result;
+	u32 data = 0;
+	u32 type, ref_addr, ref_size;
+	u32 data_section_offset;
+	u32 args_addr, src_addr, dest_addr, data_offset, length;
+	u32 idx, len, i;
+	u32 variable_array[PATCH_VAR_ARRAY_SIZE];
+
+	for(i=0; i<PATCH_VAR_ARRAY_SIZE; i++)
+		variable_array[i] = 0;
+
+	//total_patch_len = patch[1];
+	//standard = patch[2];
+	idx = 3;
+	args_addr = patch[idx++];
+	data_section_offset = patch[idx++];
+	/* reserved length */
+	len = patch[idx++];
+	idx += len;
+	/* script length */
+	len = patch[idx++];
+	len += idx;
+
+	while (idx < len) {
+		num_cmd_words = patch[idx++];
+		next_cmd_idx = idx + num_cmd_words - 1;
+		num_cond_words = patch[idx++];
+		if (num_cond_words == 0) {
+			condition = 1;
+		} else {
+			for (i = 0; i < num_cond_words; i++) {
+				operation = patch[idx++];
+				value = patch[idx++];
+				unary_op = (operation >> 8) & 0xff;
+				binary_op = operation & 0xff;
+				addr_mode_op = ((operation >> 16) & 0x3);
+
+				if ((addr_mode_op == PATCH_OP_ADDR_MODE_VAR_IDX) &&
+				    (binary_op != PATCH_OP_BINARY_STORE)) {
+					value = variable_array[value]; //grab variable value
+				}
+
+				switch(unary_op) {
+				case PATCH_OP_UNARY_LOGICAL_NEGATE:
+					value = !value;
+					break;
+				case PATCH_OP_UNARY_BITWISE_NEGATE:
+					value = ~value;
+					break;
+				default:
+					break;
+				}
+				switch(binary_op) {
+				case PATCH_OP_BINARY_LOAD:
+					condition = value;
+					break;
+				case PATCH_OP_BINARY_STORE:
+					variable_array[value] = condition;
+					break;
+				case PATCH_OP_BINARY_AND:
+					condition = condition && value;
+					break;
+				case PATCH_OP_BINARY_OR:
+					condition = condition || value;
+					break;
+				case PATCH_OP_BINARY_BITWISE_AND:
+					condition = condition & value;
+					break;
+				case PATCH_OP_BINARY_BITWISE_OR:
+					condition = condition | value;
+					break;
+				case PATCH_OP_BINARY_EQUALS:
+					condition = condition == value;
+					break;
+				case PATCH_OP_BINARY_NOT_EQUALS:
+					condition = condition != value;
+					break;
+				default:
+					break;
+				}
+			}
+		}
+
+		AVL6882_RD_REG32(priv, 0x29A648, &tmp_top_valid);
+		AVL6882_RD_REG32(priv, 0x0A0, &core_rdy_word);
+
+		if (condition) {
+			cmd = patch[idx++];
+			switch(cmd) {
+			case PATCH_CMD_PING:
+				ret = avl6882_exec_n_wait(priv, AVL_FW_CMD_PING);
+				num_rvs = patch[idx++];
+				i = patch[idx];
+				variable_array[i] = (ret == 0);
+				break;
+			case PATCH_CMD_VALIDATE_CRC:
+				exp_crc_val = patch[idx++];
+				src_addr = patch[idx++];
+				length = patch[idx++];
+				AVL6882_WR_REG32(priv,0x200 + rc_fw_command_args_addr_iaddr_offset, args_addr);
+				AVL6882_WR_REG32(priv,args_addr+0, src_addr);
+				AVL6882_WR_REG32(priv,args_addr+4, length);
+				ret = avl6882_exec_n_wait(priv, AVL_FW_CMD_CALC_CRC);
+				AVL6882_RD_REG32(priv,args_addr+8, &crc_result);
+				num_rvs = patch[idx++];
+				i = patch[idx];
+				variable_array[i] = (crc_result == exp_crc_val);
+				break;
+			case PATCH_CMD_LD_TO_DEVICE:
+				length = patch[idx++];
+				dest_addr = patch[idx++];
+				data_offset = patch[idx++];
+				data_offset += data_section_offset;
+				ret = avl6882_i2c_wr_data(priv, dest_addr, &patch[data_offset], length);
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_LD_TO_DEVICE_IMM:
+				length = patch[idx++];
+				dest_addr = patch[idx++];
+				data = patch[idx++];
+				ret = avl6882_i2c_wr_reg(priv, dest_addr, data, length);
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_RD_FROM_DEVICE:
+				length = patch[idx++];
+				src_addr = patch[idx++];
+				num_rvs = patch[idx++];
+				ret = avl6882_i2c_rd_reg(priv, src_addr, &data, length);
+				i = patch[idx];
+				variable_array[i] = data;
+				break;
+			case PATCH_CMD_DMA:
+				dest_addr = patch[idx++];
+				length = patch[idx++];
+				if (length > 0)
+					ret = avl6882_i2c_wr_data(priv, dest_addr, &patch[idx], length * 3);
+				AVL6882_WR_REG32(priv,0x200 + rc_fw_command_args_addr_iaddr_offset, dest_addr);
+				ret = avl6882_exec_n_wait(priv,AVL_FW_CMD_DMA);
+				idx += length * 3;
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_DECOMPRESS:
+				type = patch[idx++];
+				src_addr = patch[idx++];
+				dest_addr = patch[idx++];
+				if(type == PATCH_CMP_TYPE_ZLIB) {
+					ref_addr = patch[idx++];
+					ref_size = patch[idx++];
+				}
+				AVL6882_WR_REG32(priv,0x200 + rc_fw_command_args_addr_iaddr_offset, args_addr);
+				AVL6882_WR_REG32(priv,args_addr+0, type);
+				AVL6882_WR_REG32(priv,args_addr+4, src_addr);
+				AVL6882_WR_REG32(priv,args_addr+8, dest_addr);
+				if(type == PATCH_CMP_TYPE_ZLIB) {
+					AVL6882_WR_REG32(priv,args_addr+12, ref_addr);
+					AVL6882_WR_REG32(priv,args_addr+16, ref_size);
+				}
+				ret = avl6882_exec_n_wait(priv,AVL_FW_CMD_DECOMPRESS);
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_ASSERT_CPU_RESET:
+				ret |= AVL6882_WR_REG32(priv,0x110840, 1);
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_RELEASE_CPU_RESET:
+				AVL6882_WR_REG32(priv, 0x110840, 0);
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_DMA_HW:
+				dest_addr = patch[idx++];
+				length = patch[idx++];
+				if (length > 0)
+					ret = avl6882_i2c_wr_data(priv, dest_addr, &patch[idx], length * 3);
+				i = 0;
+				do {
+					if (i++ > DMA_MAX_TRIES)
+						return -ENODEV;
+					ret |= AVL6882_RD_REG32(priv, 0x110048, &data);
+				} while (!(0x01 & data));
+
+				if (data)
+					ret |= AVL6882_WR_REG32(priv, 0x110050, dest_addr);
+				idx += length * 3;
+				num_rvs = patch[idx++];
+				break;
+			case PATCH_CMD_SET_COND_IMM:
+				data = patch[idx++];
+				num_rvs = patch[idx++];
+				i = patch[idx];
+				variable_array[i] = data;
+				break;
+			default:
+				return -ENODEV;
+				break;
+			}
+			idx += num_rvs;
+		} else {
+			idx = next_cmd_idx;
+			continue;
+		}
+	}
+
+	return ret;
+}
+
+#define DEMOD_WAIT_RETRIES_BOOT	(100)
+#define DEMOD_WAIT_MS_BOOT	(20)
+static int avl6882_wait_demod_boot(struct avl6882_priv *priv)
+{
+	int ret, retry = DEMOD_WAIT_RETRIES_BOOT;
+	u32 ready_code = 0;
+	u32 status = 0;
+
+	do {
+		ret = AVL6882_RD_REG32(priv, 0x110840, &status);
+		ret |= AVL6882_RD_REG32(priv, rs_core_ready_word_iaddr_offset, &ready_code);
+		if ((ret == 0) && (status == 0) && (ready_code == 0x5aa57ff7))
+			return ret;
+		else
+			msleep(DEMOD_WAIT_MS_BOOT);
+	} while (--retry);
+	ret = -EBUSY;
+	return ret;
+}
+
+
+/* firmware loader */
+/* TODO: change to firmware loading from /lib/firmware */
+static int avl6882_load_firmware(struct avl6882_priv *priv)
+{
+	int ret = 0;
+	u8 *fw_data;
+	u32 *patch, *ptr;
+	u32 i, fw_size;
+
+	switch (priv->delivery_system) {
+	case SYS_DVBC_ANNEX_A:
+		fw_data = AVL_Demod_Patch_DVBCFw;
+		fw_size = sizeof(AVL_Demod_Patch_DVBCFw);
+		break;
+	case SYS_DVBS:
+	case SYS_DVBS2:
+		fw_data = AVL_Demod_Patch_DVBSxFw;
+		fw_size = sizeof(AVL_Demod_Patch_DVBSxFw);
+		break;
+	case SYS_DVBT:
+	case SYS_DVBT2:
+	default:
+		fw_data = AVL_Demod_Patch_DVBTxFw;
+		fw_size = sizeof(AVL_Demod_Patch_DVBTxFw);
+		break;
+	}
+
+	fw_size &= 0xfffffffc;
+	patch = kzalloc(fw_size, GFP_KERNEL);
+	if (patch == NULL) {
+	  	ret = -ENOMEM;
+		goto err;
+	}
+
+	ptr = patch;
+	for (i = 0; i < fw_size; i += 4) {
+	  	*(ptr++) = (fw_data[i]   << 24) |
+			   (fw_data[i+1] << 16) |
+			   (fw_data[i+2] <<  8) |
+			   fw_data[i+3];
+	}
+
+	/* check valid FW */
+	if ((patch[0] & 0xf0000000) != 0x10000000) {
+		ret = -EINVAL;
+		goto err1;
+	}
+	ret |= AVL6882_WR_REG32(priv,0x110010, 1);
+
+	// Configure the PLL
+	ret |= avl6882_setup_pll(priv);
+	if (ret)
+		goto err1;
+
+	ret |= AVL6882_WR_REG32(priv, 0x0a4 + rs_core_ready_word_iaddr_offset, 0x00000000);
+	ret |= AVL6882_WR_REG32(priv, 0x110010, 0);
+
+	if ((patch[0] & 0xff) == 1) /* patch version */
+		ret |= avl6882_patch_demod(priv, patch);
+	else
+		ret = -EINVAL;
+	if (ret)
+		return ret;
+
+	ret = avl6882_wait_demod_boot(priv);
+err1:
+	kfree(patch);
+err:
+	return ret;
+}
+
+
+
+int  ErrorStatMode_Demod( struct avl6882_priv *priv,AVL_ErrorStatConfig stErrorStatConfig )
+{
+	int r = AVL_EC_OK;
+	u64 time_tick_num = 270000 *  stErrorStatConfig.uiTimeThresholdMs;
+
+	r = AVL6882_WR_REG32(priv,0x132050 + esm_mode_offset,(u32) stErrorStatConfig.eErrorStatMode);
+	r |= AVL6882_WR_REG32(priv,0x132050 + tick_type_offset,(u32) stErrorStatConfig.eAutoErrorStatType);
+
+	r |= AVL6882_WR_REG32(priv,0x132050 + time_tick_low_offset, (u32) (time_tick_num));
+	r |= AVL6882_WR_REG32(priv,0x132050 + time_tick_high_offset, (u32) (time_tick_num >> 32));
+
+	r |= AVL6882_WR_REG32(priv,0x132050 + byte_tick_low_offset, stErrorStatConfig.uiTimeThresholdMs);
+	r |= AVL6882_WR_REG32(priv,0x132050 + byte_tick_high_offset, 0);//high 32-bit is not used
+
+	if(stErrorStatConfig.eErrorStatMode == AVL_ERROR_STAT_AUTO)//auto mode
+	{
+		//reset auto error stat
+		r |= AVL6882_WR_REG32(priv,0x132050 + tick_clear_offset,0);
+		r |= AVL6882_WR_REG32(priv,0x132050 + tick_clear_offset,1);
+		r |= AVL6882_WR_REG32(priv,0x132050 + tick_clear_offset,0);
+	}
+
+	return (r);
+}
+
+
+int  ResetPER_Demod(  struct avl6882_priv *priv)
+{
+	int r = AVL_EC_OK;
+	u32 uiTemp = 0;
+
+	r |= AVL6882_RD_REG32(priv,0x132050 + esm_cntrl_offset, &uiTemp);
+	uiTemp |= 0x00000001;
+	r |= AVL6882_WR_REG32(priv,0x132050 + esm_cntrl_offset, uiTemp);
+
+	r |= AVL6882_RD_REG32(priv,0x132050 + esm_cntrl_offset, &uiTemp);
+	uiTemp |= 0x00000008;
+	r |= AVL6882_WR_REG32(priv,0x132050 + esm_cntrl_offset, uiTemp);
+	uiTemp |= 0x00000001;
+	r |= AVL6882_WR_REG32(priv,0x132050 + esm_cntrl_offset, uiTemp);
+	uiTemp &= 0xFFFFFFFE;
+	r |= AVL6882_WR_REG32(priv,0x132050 + esm_cntrl_offset, uiTemp);
+
+	return r;
+}
+
+static int InitErrorStat_Demod( struct avl6882_priv *priv )
+{
+	int r = AVL_EC_OK;
+	AVL_ErrorStatConfig stErrorStatConfig;
+
+	stErrorStatConfig.eErrorStatMode = AVL_ERROR_STAT_AUTO;
+	stErrorStatConfig.eAutoErrorStatType = AVL_ERROR_STAT_TIME;
+	stErrorStatConfig.uiTimeThresholdMs = 3000;
+	stErrorStatConfig.uiNumberThresholdByte = 0;
+
+	r = ErrorStatMode_Demod(priv,stErrorStatConfig);
+	r |= ResetPER_Demod(priv);
+
+	return r;
+}
+
+
+
+
+
+int  DVBSx_Diseqc_Initialize_Demod( struct avl6882_priv *priv,AVL_Diseqc_Para *pDiseqcPara)
+{
+	int r = AVL_EC_OK;
+	u32 i1 = 0;
+
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_srst_offset, 1);
+
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_samp_frac_n_offset, 2000000); 	  //2M=200*10kHz
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_samp_frac_d_offset, 166666667);  //uiDDCFrequencyHz  166666667
+
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tone_frac_n_offset, ((pDiseqcPara->uiToneFrequencyKHz)<<1));
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tone_frac_d_offset, (166666667/1000));//uiDDCFrequencyHz  166666667
+
+	// Initialize the tx_control
+	r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+	i1 &= 0x00000300;
+	i1 |= 0x20; 	//reset tx_fifo
+	i1 |= ((u32)(pDiseqcPara->eTXGap) << 6);
+	i1 |= ((u32)(pDiseqcPara->eTxWaveForm) << 4);
+	i1 |= (1<<3);			//enable tx gap.
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+	i1 &= ~(0x20);	//release tx_fifo reset
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+	// Initialize the rx_control
+	i1 = ((u32)(pDiseqcPara->eRxWaveForm) << 2);
+	i1 |= (1<<1);	//active the receiver
+	i1 |= (1<<3);	//envelop high when tone present
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_rx_cntrl_offset, i1);
+	i1 = (u32)(pDiseqcPara->eRxTimeout);
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_rx_msg_tim_offset, i1);
+
+	r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_srst_offset, 0);
+
+	if( AVL_EC_OK == r )
+	{
+		priv->config->eDiseqcStatus = AVL_DOS_Initialized;
+	}
+
+	return (r);
+}
+
+
+static int avl6882_init_dvbs(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+	AVL_Diseqc_Para stDiseqcConfig;
+
+	ret = AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_int_mpeg_clk_MHz_saddr_offset,27000);
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_int_fec_clk_MHz_saddr_offset,25000);
+
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_int_adc_clk_MHz_saddr_offset,12500);// uiADCFrequencyHz  125000000
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_int_dmd_clk_MHz_saddr_offset,166666667/10000); //uiDDCFrequencyHz  166666667
+
+	ret |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_rfagc_pol_iaddr_offset,AVL_AGC_INVERTED);
+
+	ret |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_format_iaddr_offset, AVL_OFFBIN);//Offbin
+	ret |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_input_iaddr_offset, AVL_ADC_IN);//ADC in
+
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_IF_Offset_10kHz_saddr_offset,0);
+
+	/* enble agc */
+	ret |= AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_AGC_DVBS, 6);
+
+	stDiseqcConfig.eRxTimeout = AVL_DRT_150ms;
+	stDiseqcConfig.eRxWaveForm = AVL_DWM_Normal;
+	stDiseqcConfig.uiToneFrequencyKHz = 22;
+	stDiseqcConfig.eTXGap = AVL_DTXG_15ms;
+	stDiseqcConfig.eTxWaveForm = AVL_DWM_Normal;
+
+	ret |= DVBSx_Diseqc_Initialize_Demod(priv, &stDiseqcConfig);
+	return ret;
+}
+
+
+static int avl6882_init_dvbc(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+
+	ret = AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_dmd_clk_Hz_iaddr_offset, 250000000);
+	ret |= AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_fec_clk_Hz_iaddr_offset, 250000000);
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_rfagc_pol_caddr_offset,AVL_AGC_NORMAL);
+	ret |= AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_if_freq_Hz_iaddr_offset, 5000000);
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_adc_sel_caddr_offset, (u8) AVL_IF_Q);
+	ret |= AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_symbol_rate_Hz_iaddr_offset, 6875000);
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_j83b_mode_caddr_offset, AVL_DVBC_J83A);
+
+	//DDC configuration
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_input_format_caddr_offset, AVL_ADC_IN); //ADC in
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_input_select_caddr_offset, AVL_OFFBIN); //RX_OFFBIN
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_tuner_type_caddr_offset, AVL_DVBC_IF); //IF
+
+	//ADC configuration
+	ret |= AVL6882_WR_REG8(priv, 0x600 + rc_DVBC_adc_use_pll_clk_caddr_offset, 0);
+	ret |= AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_sample_rate_Hz_iaddr_offset, 30000000);
+
+	/* enable agc */
+    	ret |= AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_AGC_DVBTC, 6);
+
+	return ret;
+}
+
+
+static int avl6882_init_dvbt(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+
+	ret = AVL6882_WR_REG32(priv, 0xa00 + rc_DVBTx_sample_rate_Hz_iaddr_offset, 30000000);
+	ret |= AVL6882_WR_REG32(priv, 0xa00 + rc_DVBTx_mpeg_clk_rate_Hz_iaddr_offset, 270000000);
+
+	/* DDC configuration */
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_input_format_caddr_offset, AVL_OFFBIN);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_input_select_caddr_offset, AVL_ADC_IN);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_tuner_type_caddr_offset, AVL_DVBTX_REAL_IF);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_rf_agc_pol_caddr_offset, 0);
+	ret |= AVL6882_WR_REG32(priv, 0xa00 + rc_DVBTx_nom_carrier_freq_Hz_iaddr_offset, 5000000);
+
+	/* ADC configuration */
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_adc_sel_caddr_offset, (u8)AVL_IF_Q);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_adc_use_pll_clk_caddr_offset, 0);
+
+	/* enable agc */
+    	ret |= AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_AGC_DVBTC, 6);
+	return ret;
+}
+
+
+static int avl6882_read_status(struct dvb_frontend *fe, enum fe_status *status)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+	u32 reg;
+
+	*status = 0;
+
+	switch (priv->delivery_system) {
+	case SYS_DVBC_ANNEX_A:
+		ret = AVL6882_RD_REG32(priv,0x400 + rs_DVBC_mode_status_iaddr_offset, &reg);
+		if ((reg & 0xff) == 0x15)
+			reg = 1;
+		else
+		  	reg = 0;
+		break;
+	case SYS_DVBS:
+	case SYS_DVBS2:
+		ret = AVL6882_RD_REG16(priv, 0xc00 + rs_DVBSx_fec_lock_saddr_offset, &reg);
+		break;
+	case SYS_DVBT:
+	case SYS_DVBT2:
+	default:
+		ret = AVL6882_RD_REG8(priv, 0x800 + rs_DVBTx_fec_lock_caddr_offset, &reg);
+		break;
+	}
+	if (ret) {
+	  	*status = 0;
+		return ret;
+	}
+
+	if (reg)
+		*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
+			FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+
+	return ret;
+}
+
+
+
+
+static int avl6882_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+
+	dev_dbg(&priv->i2c->dev, "%s: %d\n", __func__, enable);
+
+	if (enable) {
+		ret = AVL6882_WR_REG32(priv,0x118000 + tuner_i2c_bit_rpt_cntrl_offset, 0x07);
+		ret = AVL6882_WR_REG32(priv,0x118000 + tuner_i2c_bit_rpt_cntrl_offset, 0x07);
+	} else
+		ret = AVL6882_WR_REG32(priv,0x118000 + tuner_i2c_bit_rpt_cntrl_offset, 0x06);
+
+	return ret;
+}
+
+
+static int avl6882_set_dvbs(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+	int ret;
+
+	//printk("[avl6882_set_dvbs] Freq:%d Mhz,sym:%d Khz\n", c->frequency, c->symbol_rate);
+
+	ret = AVL6882_WR_REG16(priv, 0xc00 + rs_DVBSx_fec_lock_saddr_offset, 0);
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_decode_mode_saddr_offset, 0x14);
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_fec_bypass_coderate_saddr_offset, 0); //DVBS auto lock
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_iq_mode_saddr_offset, 1); //enable spectrum auto detection
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_decode_mode_saddr_offset, 0x14);
+	ret |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_fec_bypass_coderate_saddr_offset, 0);
+	ret |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_int_sym_rate_MHz_iaddr_offset, c->symbol_rate);
+	ret |= avl6882_exec_n_wait(priv,AVL_FW_CMD_ACQUIRE);
+	return ret;
+}
+
+
+static int avl6882_set_dvbc(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+	int ret;
+
+	//printk("[avl6882_set_dvbc] Freq:%d Mhz,sym:%d\n", c->frequency, c->symbol_rate);
+
+	ret = AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_qam_mode_scan_control_iaddr_offset, 0x0101);
+	ret |= AVL6882_WR_REG32(priv, 0x600 + rc_DVBC_symbol_rate_Hz_iaddr_offset, c->symbol_rate);
+	ret |= avl6882_exec_n_wait(priv, AVL_FW_CMD_ACQUIRE);
+	return ret;
+}
+
+
+static int avl6882_set_dvbt(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+	u32 bw_fft;
+	int ret;
+
+	//printk("[avl6882_set_dvbtx] Freq:%d bw:%d\n", c->frequency, c->bandwidth_hz);
+
+	/* set bandwidth */
+	if(c->bandwidth_hz <= 1700000) {
+		bw_fft = 1845070;
+	} else if(c->bandwidth_hz <= 5000000) {
+		bw_fft = 5714285;
+	} else if(c->bandwidth_hz <= 6000000) {
+		bw_fft = 6857143;
+	} else if(c->bandwidth_hz <= 7000000) {
+		bw_fft = 8000000;
+	} else { // if(c->bandwidth_hz <= 8000) {
+		bw_fft = 9142857;
+	}
+    	ret = AVL6882_WR_REG32(priv, 0xa00 + rc_DVBTx_fund_rate_Hz_iaddr_offset, bw_fft);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_l1_proc_only_caddr_offset, 0);
+
+	/* spectrum inversion */
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_spectrum_invert_caddr_offset, AVL_SPECTRUM_AUTO);
+
+	switch (c->delivery_system) {
+	case SYS_DVBT:
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_acquire_mode_caddr_offset, (u8) AVL_DVBTx_LockMode_T_ONLY);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_dvbt_layer_select_caddr_offset, 0);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_data_PLP_ID_caddr_offset, 0);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_ID_caddr_offset, 0);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_present_caddr_offset, 0);
+		break;
+	case SYS_DVBT2:
+	default:
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_acquire_mode_caddr_offset, AVL_DVBTx_LockMode_ALL);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_data_PLP_ID_caddr_offset, c->stream_id);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_ID_caddr_offset, 0);
+		ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_present_caddr_offset, 2);
+		break;
+	}
+	ret |= avl6882_exec_n_wait(priv, AVL_FW_CMD_ACQUIRE);
+	return ret;
+}
+
+static int avl6882_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+	//printk("%s()\n", __func__);
+	*ucblocks = 0x00;
+	return 0;
+}
+
+static void avl6882_release(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	//printk("%s()\n", __func__);
+	kfree(priv);
+}
+
+static int avl6882_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+	//printk("%s()\n", __func__);
+	return 0;
+}
+
+static int avl6882_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
+{
+	//printk("%s()\n", __func__);
+	return 0;
+}
+
+static int avl6882_set_tone(struct dvb_frontend* fe, enum fe_sec_tone_mode tone)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+	u32 reg;
+
+	//printk("set tone: %d\n",tone);
+
+	ret = AVL6882_RD_REG32(priv, 0x16c000 + hw_diseqc_tx_cntrl_offset, &reg);
+	if (ret)
+		return ret;
+
+	switch(tone) {
+	case SEC_TONE_ON:
+		reg &= 0xfffffff8;
+		reg |= 0x3;	// continuous mode
+		reg |= (1<<10);	// on
+		break;
+	case SEC_TONE_OFF:
+		reg &= 0xfffff3ff;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, reg);
+}
+
+static int avl6882_set_voltage(struct dvb_frontend* fe, enum fe_sec_voltage voltage)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	u32 pwr, vol;
+	int ret;
+
+	//printk("set voltage: %d\n",voltage);
+
+	switch (voltage) {
+	case SEC_VOLTAGE_OFF:
+		pwr = GPIO_1;
+		vol = GPIO_0;
+		break;
+	case SEC_VOLTAGE_13:
+		//power on
+		pwr = GPIO_0;
+		vol = GPIO_0;
+		break;
+	case SEC_VOLTAGE_18:
+		//power on
+		pwr = GPIO_0;
+		vol = GPIO_Z;
+		break;
+	default:
+		return -EINVAL;
+	}
+	ret = AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_LNB_PWR, pwr);
+	ret |= AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_LNB_VOLTAGE, vol);
+	return ret;
+}
+
+static int avl6882_init(struct dvb_frontend *fe)
+{
+	return 0;
+}
+
+
+#define I2C_RPT_DIV ((0x2A)*(250000)/(240*1000))	//m_CoreFrequency_Hz 250000000
+
+static int avl6882_set_dvbmode(struct dvb_frontend *fe,
+		enum fe_delivery_system delsys)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	int ret;
+	u32 reg;
+
+	/* these modes use the same fw / config */
+	if (delsys == SYS_DVBS2)
+		delsys = SYS_DVBS;
+	else if (delsys == SYS_DVBT2)
+		delsys = SYS_DVBT;
+
+	/* already in desired mode */
+	if (priv->delivery_system == delsys)
+		return 0;
+
+	priv->delivery_system = delsys;
+	//printk("initing demod for delsys=%d\n", delsys);
+
+	ret = avl6882_load_firmware(priv);
+
+	// Load the default configuration
+	ret |= avl6882_exec_n_wait(priv, AVL_FW_CMD_LD_DEFAULT);
+	ret |= avl6882_exec_n_wait(priv, AVL_FW_CMD_INIT_SDRAM);
+	ret |= avl6882_exec_n_wait(priv, AVL_FW_CMD_INIT_ADC);
+
+	switch (priv->delivery_system) {
+	case SYS_DVBC_ANNEX_A:
+		ret |= avl6882_init_dvbc(fe);
+		break;
+	case SYS_DVBS:
+	case SYS_DVBS2:
+		ret |= avl6882_init_dvbs(fe);
+		break;
+	case SYS_DVBT:
+	case SYS_DVBT2:
+	default:
+		ret |= avl6882_init_dvbt(fe);
+		break;
+	}
+
+	/* set gpio / turn off lnb, set 13V */
+	ret = AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_LNB_PWR, GPIO_1);
+	ret |= AVL6882_WR_REG32(priv, REG_GPIO_BASE + GPIO_LNB_VOLTAGE, GPIO_0);
+
+	/* set TS mode */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_serial_caddr_offset, AVL_TS_PARALLEL);
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_clock_edge_caddr_offset, AVL_MPCM_RISING);
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_enable_ts_continuous_caddr_offset, AVL_TS_CONTINUOUS_ENABLE);
+
+	/* TS serial pin */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_serial_outpin_caddr_offset, AVL_MPSP_DATA0);
+	/* TS serial order */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_serial_msb_caddr_offset, AVL_MPBO_MSB);
+	/* TS serial sync pulse */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_sync_pulse_caddr_offset, AVL_TS_SERIAL_SYNC_1_PULSE);
+	/* TS error pol */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_error_polarity_caddr_offset, AVL_MPEP_Normal);
+	/* TS valid pol */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_valid_polarity_caddr_offset, AVL_MPVP_Normal);
+	/* TS packet len */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_packet_len_caddr_offset, AVL_TS_188);
+	/* TS parallel order */
+	ret |= AVL6882_WR_REG8(priv,0x200 + rc_ts_packet_order_caddr_offset, AVL_TS_PARALLEL_ORDER_NORMAL);
+	/* TS parallel phase */
+	ret |= AVL6882_WR_REG8(priv,0x200 + ts_clock_phase_caddr_offset, AVL_TS_PARALLEL_PHASE_0);
+
+	/* TS output enable */
+	ret |= AVL6882_WR_REG32(priv, REG_TS_OUTPUT, TS_OUTPUT_ENABLE);
+
+	/* init tuner i2c repeater */
+	/* hold in reset */
+	ret |= AVL6882_WR_REG32(priv, 0x118000 + tuner_i2c_srst_offset, 1);
+	/* close gate */
+	ret |= AVL6882_WR_REG32(priv, 0x118000 + tuner_i2c_bit_rpt_cntrl_offset, 0x6);
+	ret |= AVL6882_RD_REG32(priv, 0x118000 + tuner_i2c_cntrl_offset, &reg);
+	reg &= 0xfffffffe;
+	ret |= AVL6882_WR_REG32(priv, 0x118000 + tuner_i2c_cntrl_offset, reg);
+	/* set bit clock */
+	ret |= AVL6882_WR_REG32(priv, 0x118000 + tuner_i2c_bit_rpt_clk_div_offset, I2C_RPT_DIV);
+	/* release from reset */
+	ret |= AVL6882_WR_REG32(priv, 0x118000 + tuner_i2c_srst_offset, 0);
+
+	ret |= InitErrorStat_Demod(priv);
+
+	if (ret) {
+		dev_err(&priv->i2c->dev, "%s: demod init failed",
+				KBUILD_MODNAME);
+	}
+
+	return ret;
+}
+
+static int avl6882_sleep(struct dvb_frontend *fe)
+{
+	//printk("%s()\n", __func__);
+	return 0;
+}
+
+
+static int avl6882fe_strength(struct dvb_frontend *fe, u16 *signal_strength)
+{
+	*signal_strength = 0x1234;
+	return 0;
+}
+
+static int avl6882fe_snr(struct dvb_frontend *fe, u16 *snr)
+{
+	*snr = 0x1234;
+	return 0;
+}
+
+static int avl6882_diseqc(struct dvb_frontend *fe,
+	struct dvb_diseqc_master_cmd *d)
+{
+	//printk("%s()\n", __func__);
+	return 0;
+}
+
+static int avl6882fe_algo(struct dvb_frontend *fe)
+{
+	return DVBFE_ALGO_HW;
+}
+
+static int avl6882_set_frontend(struct dvb_frontend *fe)
+{
+	struct avl6882_priv *priv = fe->demodulator_priv;
+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+	u32 demod_mode;
+	int ret;
+
+	//printk("%s()\n", __func__);
+
+	/* check that mode is correctly set */
+	ret = AVL6882_RD_REG32(priv, 0x200 + rs_current_active_mode_iaddr_offset, &demod_mode);
+	if (ret)
+		return ret;
+
+	/* setup tuner */
+	if (fe->ops.tuner_ops.set_params) {
+		if (fe->ops.i2c_gate_ctrl)
+			fe->ops.i2c_gate_ctrl(fe, 1);
+		ret = fe->ops.tuner_ops.set_params(fe);
+		if (fe->ops.i2c_gate_ctrl)
+			fe->ops.i2c_gate_ctrl(fe, 0);
+
+		if (ret)
+			return ret;
+	}
+
+	switch (c->delivery_system) {
+	case SYS_DVBT:
+	case SYS_DVBT2:
+		if (demod_mode != AVL_DVBTX) {
+			dev_err(&priv->i2c->dev, "%s: failed to enter DVBTx mode",
+				KBUILD_MODNAME);
+			ret = -EAGAIN;
+			break;
+		}
+		ret = avl6882_set_dvbt(fe);
+		break;
+	case SYS_DVBC_ANNEX_A:
+		if (demod_mode != AVL_DVBC) {
+			dev_err(&priv->i2c->dev, "%s: failed to enter DVBC mode",
+				KBUILD_MODNAME);
+			ret = -EAGAIN;
+			break;
+		}
+		ret = avl6882_set_dvbc(fe);
+		break;
+	case SYS_DVBS:
+	case SYS_DVBS2:
+		if (demod_mode != AVL_DVBSX) {
+			dev_err(&priv->i2c->dev, "%s: failed to enter DVBSx mode",
+				KBUILD_MODNAME);
+			ret = -EAGAIN;
+			break;
+		}
+		ret = avl6882_set_dvbs(fe);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int avl6882_tune(struct dvb_frontend *fe, bool re_tune,
+	unsigned int mode_flags, unsigned int *delay, enum fe_status *status)
+{
+	*delay = HZ / 5;
+	if (re_tune) {
+		int ret = avl6882_set_frontend(fe);
+		if (ret)
+			return ret;
+	}
+	return avl6882_read_status(fe, status);
+}
+
+static int avl6882_get_frontend(struct dvb_frontend *fe)
+{
+	return 0;
+}
+
+static int avl6882_set_property(struct dvb_frontend *fe,
+		struct dtv_property *p)
+{
+	int ret = 0;
+
+	switch (p->cmd) {
+	case DTV_DELIVERY_SYSTEM:
+		ret = avl6882_set_dvbmode(fe, p->u.data);
+		switch (p->u.data) {
+		case SYS_DVBC_ANNEX_A:
+			fe->ops.info.frequency_min = 47000000;
+			fe->ops.info.frequency_max = 862000000;
+			fe->ops.info.frequency_stepsize = 62500;
+			break;
+		case SYS_DVBS:
+		case SYS_DVBS2:
+			fe->ops.info.frequency_min = 950000;
+			fe->ops.info.frequency_max = 2150000;
+			fe->ops.info.frequency_stepsize = 0;
+			break;
+		case SYS_DVBT:
+		case SYS_DVBT2:
+		default:
+			fe->ops.info.frequency_min = 174000000;
+			fe->ops.info.frequency_max = 862000000;
+			fe->ops.info.frequency_stepsize = 250000;
+			break;
+		}
+
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+
+static struct dvb_frontend_ops avl6882_ops = {
+	.delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A, SYS_DVBS, SYS_DVBS2},
+	.info = {
+		.name			= "Availink AVL6882",
+		.frequency_min		= 0,
+		.frequency_max		= 0,
+		.frequency_stepsize	= 0,
+		.frequency_tolerance	= 0,
+		.symbol_rate_min	= 1000000,
+		.symbol_rate_max	= 45000000,
+		.caps = FE_CAN_FEC_1_2                 |
+			FE_CAN_FEC_2_3                 |
+			FE_CAN_FEC_3_4                 |
+			FE_CAN_FEC_4_5                 |
+			FE_CAN_FEC_5_6                 |
+			FE_CAN_FEC_6_7                 |
+			FE_CAN_FEC_7_8                 |
+			FE_CAN_FEC_AUTO                |
+			FE_CAN_QPSK                    |
+			FE_CAN_QAM_16                  |
+			FE_CAN_QAM_32                  |
+			FE_CAN_QAM_64                  |
+			FE_CAN_QAM_128                 |
+			FE_CAN_QAM_256                 |
+			FE_CAN_QAM_AUTO                |
+			FE_CAN_TRANSMISSION_MODE_AUTO  |
+			FE_CAN_GUARD_INTERVAL_AUTO     |
+			FE_CAN_HIERARCHY_AUTO          |
+			FE_CAN_MUTE_TS                 |
+			FE_CAN_2G_MODULATION           |
+			FE_CAN_MULTISTREAM             |
+			FE_CAN_INVERSION_AUTO
+	},
+
+	.release			= avl6882_release,
+	.init				= avl6882_init,
+
+	.sleep				= avl6882_sleep,
+	.i2c_gate_ctrl			= avl6882_i2c_gate_ctrl,
+
+	.read_status			= avl6882_read_status,
+	.read_ber = avl6882_read_ber,
+	.read_signal_strength = avl6882fe_strength,
+	.read_snr = avl6882fe_snr,
+	.read_ucblocks = avl6882_read_ucblocks,
+	.set_tone			= avl6882_set_tone,
+	.set_voltage			= avl6882_set_voltage,
+	.diseqc_send_master_cmd = avl6882_diseqc,
+	.diseqc_send_burst = avl6882_burst,
+	.get_frontend_algo		= avl6882fe_algo,
+	.tune				= avl6882_tune,
+
+	.set_property			= avl6882_set_property,
+//	.get_property = avl6882_get_property,
+	.set_frontend			= avl6882_set_frontend,
+	.get_frontend = avl6882_get_frontend,
+};
+
+
+struct dvb_frontend *avl6882_attach(struct avl6882_config *config,
+					struct i2c_adapter *i2c)
+{
+	struct avl6882_priv *priv;
+	int ret;
+	u32 id, fid;
+
+	priv = kzalloc(sizeof(struct avl6882_priv), GFP_KERNEL);
+	if (priv == NULL)
+		goto err;
+
+	memcpy(&priv->frontend.ops, &avl6882_ops,
+		sizeof(struct dvb_frontend_ops));
+
+	priv->frontend.demodulator_priv = priv;
+	priv->config = config;
+	priv->i2c = i2c;
+	priv->g_nChannel_ts_total = 0,
+	priv->delivery_system = -1;
+
+	/* get chip id */
+	ret = AVL6882_RD_REG32(priv, 0x108000, &id);
+	/* get chip family id */
+	ret |= AVL6882_RD_REG32(priv, 0x40000, &fid);
+	if (ret) {
+		dev_err(&priv->i2c->dev, "%s: attach failed reading id",
+				KBUILD_MODNAME);
+		goto err1;
+	}
+
+	if (fid != 0x68624955) {
+		dev_err(&priv->i2c->dev, "%s: attach failed family id mismatch",
+				KBUILD_MODNAME);
+		goto err1;
+	}
+
+	dev_info(&priv->i2c->dev, "%s: found id=0x%x " \
+				"family_id=0x%x", KBUILD_MODNAME, id, fid);
+
+	return &priv->frontend;
+
+err1:
+	kfree(priv);
+err:
+	return NULL;
+}
+EXPORT_SYMBOL(avl6882_attach);
+
+MODULE_DESCRIPTION("Availink AVL6882 DVB demodulator driver");
+MODULE_AUTHOR("Luis Alves (ljalvs@gmail.com)");
+MODULE_LICENSE("GPL");
+
+
+
+
+#if 0
+static int AVL_Demod_DVBSx_Diseqc_SendModulationData(struct avl6882_priv *priv, AVL_puchar pucBuff, u8 ucSize)
+{
+	int r = 0;
+	u32 i1 = 0;
+	u32 i2 = 0;
+	//u8 pucBuffTemp[8] = {0};
+	u8 Continuousflag = 0;
+	u16 uiTempOutTh = 0;
+
+	if (ucSize > 8) {
+		r = AVL_EC_WARNING;
+	} else {
+		if (priv->config->eDiseqcStatus == AVL_DOS_InContinuous) {
+			r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+			if ((i1>>10) & 0x01) {
+				Continuousflag = 1;
+				i1 &= 0xfffff3ff;
+				r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+				msleep(Diseqc_delay);		//delay 20ms
+			}
+		}
+		//reset rx_fifo
+		r |= AVL6882_RD_REG32(priv, 0x16c000 + hw_diseqc_rx_cntrl_offset, &i2);
+		r |= AVL6882_WR_REG32(priv, 0x16c000 + hw_diseqc_rx_cntrl_offset, (i2|0x01));
+		r |= AVL6882_WR_REG32(priv, 0x16c000 + hw_diseqc_rx_cntrl_offset, (i2&0xfffffffe));
+
+		r |= AVL6882_RD_REG32(priv, 0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+		i1 &= 0xfffffff8;	//set to modulation mode and put it to FIFO load mode
+		r |= AVL6882_WR_REG32(priv, 0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+		for (i2=0; i2 < ucSize; i2++) {
+			r |= AVL6882_WR_REG32(priv, 0x16c000 + hw_tx_fifo_map_offset, pucBuff[i2]);
+		}
+#if 0
+		//trunk address
+		ChunkAddr_Demod(0x16c000 + hw_tx_fifo_map_offset, pucBuffTemp);
+		pucBuffTemp[3] = 0;
+		pucBuffTemp[4] = 0;
+		pucBuffTemp[5] = 0;
+		for( i2=0; i2<ucSize; i2++ ) {
+			pucBuffTemp[6] = pucBuff[i2];
+
+			r |= II2C_Write_Demod(priv, pucBuffTemp, 7);
+		}
+#endif
+
+		i1 |= (1<<2);  //start fifo transmit.
+		r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+		if (AVL_EC_OK == r) {
+			priv->config->eDiseqcStatus = AVL_DOS_InModulation;
+		}
+		do {
+			msleep(1);
+			if (++uiTempOutTh > 500) {
+				r |= AVL_EC_TIMEOUT;
+				return(r);
+			}
+			r = AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_st_offset, &i1);
+		} while (1 != ((i1 & 0x00000040) >> 6));
+
+		msleep(Diseqc_delay);		//delay 20ms
+		if (Continuousflag == 1) {			//resume to send out wave
+			//No data in FIFO
+			r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+			i1 &= 0xfffffff8;
+			i1 |= 0x03; 	//switch to continuous mode
+			r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+			//start to send out wave
+			i1 |= (1<<10);
+			r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+			if (AVL_EC_OK == r) {
+				priv->config->eDiseqcStatus = AVL_DOS_InContinuous;
+			}
+		}
+	}
+	return (r);
+}
+
+
+int  AVL_Demod_DVBSx_Diseqc_GetTxStatus( struct avl6882_priv *priv, AVL_Diseqc_TxStatus * pTxStatus)
+{
+	int r = 0;
+	u32 i1 = 0;
+
+
+
+	if( (AVL_DOS_InModulation == priv->config->eDiseqcStatus) || (AVL_DOS_InTone == priv->config->eDiseqcStatus) )
+	{
+		r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_st_offset, &i1);
+		pTxStatus->m_TxDone = (u8)((i1 & 0x00000040)>>6);
+		pTxStatus->m_TxFifoCount = (u8)((i1 & 0x0000003c)>>2);
+	}
+	else
+	{
+		r |= AVL_EC_GENERAL_FAIL;
+	}
+
+	return (r);
+}
+
+
+void AVL_SX_DiseqcSendCmd(struct avl6882_priv *priv, AVL_puchar pCmd, u8 CmdSize)
+{
+	int r = AVL_EC_OK;
+	struct AVL_Diseqc_TxStatus TxStatus;
+
+	r = AVL_Demod_DVBSx_Diseqc_SendModulationData(priv,pCmd, CmdSize);
+	if(r != AVL_EC_OK) {
+		printk("AVL_SX_DiseqcSendCmd failed !\n");
+	} else {
+		do {
+			msleep(5);
+			r |= AVL_Demod_DVBSx_Diseqc_GetTxStatus(priv,&TxStatus);
+		} while(TxStatus.m_TxDone != 1);
+		if (r == AVL_EC_OK ) {
+		} else {
+			printk("AVL_SX_DiseqcSendCmd Err. !\n");
+		}
+	}
+}
+
+#endif
+
+
+
+
+
+
+
+
+#if 0
+static int AVL_Demod_DVBSx_GetFunctionalMode( struct avl6882_priv *priv,AVL_FunctionalMode * pFunctionalMode)
+{
+	int r = AVL_EC_OK;
+	u32 uiTemp = 0;
+
+	r = AVL6882_RD_REG16(priv,0xe00 + rc_DVBSx_functional_mode_saddr_offset, &uiTemp);
+	*pFunctionalMode = (AVL_FunctionalMode)(uiTemp & 0x0001);
+
+	return(r);
+}
+
+#endif
+
+#if 0
+static int AVL_Demod_GetSNR(struct avl6882_priv *priv,u32 *snr_db)
+{
+	int r = AVL_EC_OK;
+
+	*snr_db = 0;
+
+	/* dvb-s */
+	r = AVL6882_RD_REG32(priv,0xc00 + rs_DVBSx_int_SNR_dB_iaddr_offset, snr_db);
+	if( (*puiSNR_db) > 10000 )
+	{
+		// Not get stable SNR value yet.
+		*puiSNR_db = 0;
+	}
+
+	return (r);
+}
+#endif
+#if 0
+static int DVBSx_GetSignalQuality_Demod(struct avl6882_priv *priv, AVL_puint16 puiQuality )
+{
+	int r = AVL_EC_OK;
+	u32 uiTemp = 0;
+
+	r = DVBSx_GetSNR_Demod(priv,&uiTemp);
+	if(uiTemp > 2500) {
+		*puiQuality = 100;
+	} else {
+		*puiQuality = uiTemp*100/2500;
+	}
+
+	return r;
+}
+
+int AVL_Demod_GetSQI ( struct avl6882_priv *priv,AVL_puint16 pusSQI)
+{
+	int r = AVL_EC_OK;
+
+	*pusSQI = 0;
+	r=DVBSx_GetSignalQuality_Demod(priv,pusSQI);
+
+	return (r);
+}
+#endif
+#if 0
+int AVL_Demod_GetSSI( struct avl6882_priv *priv,AVL_puint16 pusSSI)
+{
+	int r = AVL_EC_OK;
+	u32 v;
+
+	r = AVL6882_RD_REG16(priv,0x0a4 + rs_rf_agc_saddr_offset, &v);
+	*pusSSI = (u16) v;
+
+	return (r);
+}
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+#if 0
+
+
+
+static int AVL_LockChannel_T2(struct avl6882_priv *priv, u32 Freq_Khz, u32 BandWidth_Khz, u8 T2_Profile, AVL_int32 PLP_ID)
+{
+	int ret;
+	AVL_DVBTxBandWidth nBand = AVL_DVBTx_BW_8M;
+	AVL_DVBTx_LockMode eDVBTxLockMode;
+	AVL_DVBT2_PROFILE eDVTB2Profile = (AVL_DVBT2_PROFILE) T2_Profile;
+
+	printk("[AVL_LockChannel_T2] Freq:%d Mhz,sym:%d Khz\n",Freq_Khz,BandWidth_Khz);
+
+	//return_code = r848_lock_n_wait(priv, Freq_Khz, BandWidth_Khz);
+	//AVL_Demod_DVBT2AutoLock(priv, nBand, , PLP_ID);
+
+	ret = AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_l1_proc_only_caddr_offset, 0);
+	if (eDVTB2Profile == AVL_DVBT2_PROFILE_BASE) {
+	    eDVBTxLockMode = AVL_DVBTx_LockMode_T2BASE;
+	} else if (eDVTB2Profile == AVL_DVBT2_PROFILE_LITE) {
+	    eDVBTxLockMode = AVL_DVBTx_LockMode_T2LITE;
+	} else {
+	    eDVBTxLockMode = AVL_DVBTx_LockMode_ALL;
+	}
+
+	nBand = Convert2DemodBand(BandWidth_Khz);
+	ret |= DVBTx_SetBandWidth_Demod(priv, nBand);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_acquire_mode_caddr_offset, (u8) eDVBTxLockMode);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_spectrum_invert_caddr_offset, AVL_SPECTRUM_AUTO);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_data_PLP_ID_caddr_offset, PLP_ID);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_ID_caddr_offset, 0);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_present_caddr_offset, 2);
+	ret |= avl6882_exec_n_wait(priv,AVL_FW_CMD_ACQUIRE);
+	if (ret)
+		printk("[AVL_LockChannel_DVBT2] Failed to lock the channel!\n");
+	return ret;
+}
+
+
+static int AVL_LockChannel_T(struct avl6882_priv *priv,u32 Freq_Khz,u16 BandWidth_Khz, AVL_int32 DVBT_layer_info)
+{
+	int ret;
+	AVL_DVBTxBandWidth nBand = AVL_DVBTx_BW_8M;
+
+	printk("[AVL_LockChannel_T] Freq is %d MHz, Bandwide is %d MHz, Layer Info is %d (0 : LP; 1 : HP)\n",
+			   Freq_Khz/1000, BandWidth_Khz/1000, DVBT_layer_info);
+
+	//ret = r848_lock_n_wait(priv, Freq_Khz, BandWidth_Khz);
+	nBand = Convert2DemodBand(BandWidth_Khz);
+	//AVL_Demod_DVBTAutoLock
+	ret = AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_l1_proc_only_caddr_offset, 0);
+	ret |= DVBTx_SetBandWidth_Demod(priv, nBand);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_acquire_mode_caddr_offset, (u8) AVL_DVBTx_LockMode_T_ONLY);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_spectrum_invert_caddr_offset, AVL_SPECTRUM_AUTO);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_dvbt_layer_select_caddr_offset, DVBT_layer_info);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_data_PLP_ID_caddr_offset, 0);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_ID_caddr_offset, 0);
+	ret |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_common_PLP_present_caddr_offset, 0);
+	ret |= avl6882_exec_n_wait(priv, AVL_FW_CMD_ACQUIRE);
+	if(ret)
+	    printk("[AVL_LockChannel_T] Failed to lock the channel!\n");
+
+	return ret;
+}
+
+
+
+
+static int IBase_SendRxOP_Demod(struct avl6882_priv *priv,u8 cmd)
+{
+	int ret = avl6882_wait_demod(priv);
+	if (ret)
+		return ret;
+	return AVL6882_WR_REG16(priv, 0x200 + rc_fw_command_saddr_offset, (u32) cmd);
+}
+
+int  TestSDRAM_Demod( struct avl6882_priv *priv,AVL_puint32 puiTestResult, AVL_puint32 puiTestPattern)
+{
+	int r = AVL_EC_OK;
+	u16 uiTimeDelay = 100;
+	u16 uiMaxRetries = 200;
+	u32 i=0;
+
+	r = IBase_SendRxOP_Demod(priv,AVL_FW_CMD_SDRAM_TEST);
+	if(AVL_EC_OK == r )
+	{
+
+		r |= avl6882_wait_demod(priv);
+/*		while (AVL_EC_OK != IBase_GetRxOPStatus_Demod(priv))
+		{
+			if (uiMaxRetries < i++)
+			{
+				r |= AVL_EC_RUNNING;
+				break;
+			}
+			msleep(uiTimeDelay);
+		}*/
+
+		r |= AVL6882_RD_REG32(priv,0x0a4 + rc_sdram_test_return_iaddr_offset, puiTestPattern);
+		r |= AVL6882_RD_REG32(priv,0x0a4 + rc_sdram_test_result_iaddr_offset, puiTestResult);
+	}
+
+	return r;
+}
+
+static int avl6882_demod_lock_wait(struct avl6882_priv *priv, u8 *lock_flag)
+{
+	int ret, retry = 50;
+	enum fe_status locked;
+	do {
+		ret = avl6882_read_status(&priv->frontend, &locked);
+		if (ret) {
+			*lock_flag = 0;
+			break;
+		}
+		if (locked) {
+			*lock_flag = 1;
+			break;
+		}
+		msleep(20);
+	} while (--retry);
+	return ret;
+}
+
+int AVL_Demod_DVBTxChannelScan(struct avl6882_priv *priv, AVL_DVBTxBandWidth eBandWidth, AVL_DVBTx_LockMode eLockMode)
+{
+    int r = AVL_EC_OK;
+
+    r = DVBTx_SetBandWidth_Demod(priv,eBandWidth);
+    r |= AVL6882_WR_REG8(priv,0xa00 + rc_DVBTx_acquire_mode_caddr_offset, eLockMode);
+    r |= AVL6882_WR_REG8(priv, 0xa00 + rc_DVBTx_l1_proc_only_caddr_offset, 1);
+    r |= avl6882_exec_n_wait(priv,AVL_FW_CMD_ACQUIRE);
+
+    return r;
+}
+
+
+int AVL_Demod_DVBTxGetScanInfo(struct avl6882_priv *priv, AVL_DVBTxScanInfo* pstDVBTxScanInfo)
+{
+    int r = AVL_EC_OK;
+    u32 ucTemp0 = 0;
+    u32 ucTemp1 = 0;
+    enum fe_status ucDemodLockStatus;
+
+    r = avl6882_read_status(&priv->frontend, &ucDemodLockStatus);
+    if(ucDemodLockStatus == 0)
+        return r;
+
+    r |= AVL6882_RD_REG8(priv, 0x800 + rs_DVBTx_rx_mode_caddr_offset,
+                         &ucTemp0);
+
+    pstDVBTxScanInfo->eTxStandard = (AVL_DVBTx_Standard)ucTemp0;
+
+
+    if(AVL_DVBTx_Standard_T == pstDVBTxScanInfo->eTxStandard)
+    {
+        r |= AVL6882_RD_REG8(priv, 0x8f0 + rs_DVBTx_hierarchy_caddr_offset,&ucTemp0);
+    }
+    else if(AVL_DVBTx_Standard_T2 == pstDVBTxScanInfo->eTxStandard)
+    {
+        r |= AVL6882_RD_REG8(priv,0x800 + rs_DVBTx_P1_S2_field_2_caddr_offset, &ucTemp1);
+        r |= AVL6882_RD_REG8(priv, 0x800 + rs_DVBTx_T2_profile_caddr_offset, &ucTemp0);
+    }
+
+    pstDVBTxScanInfo->ucTxInfo = ucTemp0;
+    pstDVBTxScanInfo->ucFEFInfo = ucTemp1;
+
+    return r;
+}
+
+
+
+
+static int AVL_Demod_DVBT2GetPLPList(struct avl6882_priv *priv, AVL_puchar pucPLPIndexArray, AVL_puchar pucPLPNumber)
+{
+	int r = AVL_EC_OK;
+	u32 ucTemp = 0;
+	u32 uiPLPBuffer = 0x2912b4;
+	u32 ucPLPID = 0;
+	u32 ucPLPType = 0;
+	u32 ucPLPGroupID = 0;
+	u32 i = 0;
+	u8 ucDataPLPNum = 0;
+	u32 uiDelayMS = 20;
+	u32 uiTimes = 10; //time-out window 10*20 = 200ms
+	enum fe_status ucDemodLockStatus = 0;
+
+	r = avl6882_read_status(&priv->frontend, &ucDemodLockStatus);
+	if (ucDemodLockStatus == 0) {
+		*pucPLPNumber = 0;
+		return r;
+	}
+
+	for(i = 0; i < uiTimes; i++)
+	{
+	    msleep(uiDelayMS);
+	    r |= AVL6882_RD_REG8(priv,0x800 + rs_DVBTx_plp_list_request_caddr_offset, &ucTemp);
+	    if(ucTemp == 0)
+	    {
+		break;
+	    }
+	}
+
+	if(i == uiTimes)
+	{
+	    r |= AVL_EC_GENERAL_FAIL;
+	    return (r);
+	}
+
+	r |= AVL6882_RD_REG8(priv,0x830 + rs_DVBTx_NUM_PLP_caddr_offset, &ucTemp);
+
+
+	for(i = 0; i<ucTemp; i++)
+	{
+	    r |= AVL6882_RD_REG8(priv,uiPLPBuffer++, &ucPLPID);
+	    r |= AVL6882_RD_REG8(priv,uiPLPBuffer++, &ucPLPType);
+	    r |= AVL6882_RD_REG8(priv,uiPLPBuffer++, &ucPLPGroupID);
+
+	    if(ucPLPType != 0)
+	    {
+		*(pucPLPIndexArray + ucDataPLPNum) = ucPLPID;
+		ucDataPLPNum++;
+	    }
+	}
+	*pucPLPNumber = ucDataPLPNum;
+	return (r);
+}
+
+
+static int avl6882_set_dvbt(struct dvb_frontend *fe)
+{
+
+	u32 Freq_Khz = c->frequency/1000;
+	u16 BandWidth_Khz = c->bandwidth_hz/1000;
+
+	int return_code = AVL_EC_OK;
+	AVL_DVBTxScanInfo stDVBTxScanInfo;
+	AVL_DVBTxBandWidth nBand = AVL_DVBTx_BW_8M;
+	u16 cur_index = 0;
+	u8 ucLockFlag = 0;
+	AVL_DVBT2_PROFILE ucT2Profile = AVL_DVBT2_PROFILE_UNKNOWN;
+	u8 ucDataPLPArray[255] = {0};
+	u8 ucDataPLPNumber = 0;
+	u16 i;
+
+	printk("[AVL_ChannelScan_Tx] Freq is %d MHz BW is %d MHz \n",
+			Freq_Khz/1000, BandWidth_Khz/1000);
+
+	priv->g_nChannel_ts_total = 0;
+
+	//=====Tuner Lock=====//
+	return_code = r848_lock_n_wait(priv, Freq_Khz, c->bandwidth_hz);
+	//=====Demod Lock=====//
+	nBand = Convert2DemodBand(BandWidth_Khz);
+	return_code = AVL_Demod_DVBTxChannelScan(priv, nBand, AVL_DVBTx_LockMode_ALL);
+	//=====Check Lock Status =====//
+	avl6882_demod_lock_wait(priv, &ucLockFlag);
+
+	if(ucLockFlag == 1) { //DVBTx is locked
+		return_code |= AVL_Demod_DVBTxGetScanInfo(priv, &stDVBTxScanInfo);
+		if(stDVBTxScanInfo.eTxStandard == AVL_DVBTx_Standard_T2) {
+		  	//get PLP ID list only for DVBT2 signal, not for DVBT
+			cur_index = priv->g_nChannel_ts_total;
+			return_code = AVL_Demod_DVBT2GetPLPList(priv, ucDataPLPArray, &ucDataPLPNumber);
+
+			for (i = 0; i < ucDataPLPNumber; i++) {
+				printk("[DVB-T2_Scan_Info] DATA PLP ID is %d, profile = %d\n",
+					ucDataPLPArray[i], stDVBTxScanInfo.ucTxInfo);
+
+				//save channel RF frequency
+				priv->global_channel_ts_table[cur_index].channel_freq_khz = Freq_Khz;
+				// save channel bandwidth
+				priv->global_channel_ts_table[cur_index].channel_bandwith_khz = BandWidth_Khz;
+				// save data plp id
+				priv->global_channel_ts_table[cur_index].data_plp_id = ucDataPLPArray[i];
+				// 0 - DVBT; 1 - DVBT2.
+				priv->global_channel_ts_table[cur_index].channel_type = AVL_DVBTx_Standard_T2;
+				// 0 - Base profile; 1 - Lite profile.
+				priv->global_channel_ts_table[cur_index].channel_profile = (AVL_DVBT2_PROFILE)stDVBTxScanInfo.ucTxInfo;
+				cur_index++;
+			}
+			priv->g_nChannel_ts_total = cur_index % MAX_CHANNEL_INFO;
+			if (stDVBTxScanInfo.ucFEFInfo == 1) {
+				ucT2Profile = (AVL_DVBT2_PROFILE) stDVBTxScanInfo.ucTxInfo;
+				if (ucT2Profile == AVL_DVBT2_PROFILE_BASE) {
+					//profile is base
+					//If T2 base is locked, try to lock T2 lite
+					AVL_Demod_DVBTxChannelScan(priv, nBand, AVL_DVBTx_LockMode_T2LITE);
+					ucT2Profile = AVL_DVBT2_PROFILE_LITE;
+				} else {
+					//If T2 lite is locked, try to lock T2 base
+					AVL_Demod_DVBTxChannelScan(priv, nBand, AVL_DVBTx_LockMode_T2BASE);
+					ucT2Profile = AVL_DVBT2_PROFILE_BASE;
+				}
+				avl6882_demod_lock_wait(priv, &ucLockFlag);
+				if (ucLockFlag == 1) {
+					//DVBTx is locked
+					cur_index = priv->g_nChannel_ts_total;
+					ucDataPLPNumber = 0;
+					return_code = AVL_Demod_DVBT2GetPLPList(priv, ucDataPLPArray, &ucDataPLPNumber);
+
+					// data PLP ID and common PLP ID pairing
+					for (i = 0; i < ucDataPLPNumber; i++) {
+						printk("[DVB-T2_Scan_Info] DATA PLP ID is %d, profile = %d\n",
+								ucDataPLPArray[i], ucT2Profile);
+
+						//save channel RF frequency
+						priv->global_channel_ts_table[cur_index].channel_freq_khz = Freq_Khz;
+						// save channel bandwidth
+						priv->global_channel_ts_table[cur_index].channel_bandwith_khz = BandWidth_Khz;
+						// save data plp id
+						priv->global_channel_ts_table[cur_index].data_plp_id = ucDataPLPArray[i];
+						// 0 - DVBT; 1 - DVBT2.
+						priv->global_channel_ts_table[cur_index].channel_type = AVL_DVBTx_Standard_T2;
+						// 0 - Base profile; 1 - Lite profile.
+						priv->global_channel_ts_table[cur_index].channel_profile = ucT2Profile;
+
+						cur_index++;
+					}
+					priv->g_nChannel_ts_total = cur_index % MAX_CHANNEL_INFO;
+				}
+			} else {
+				printk("Lock DVB-T2: No FEFInfo\n");
+			}
+		} else {
+			// DVBT
+			cur_index = priv->g_nChannel_ts_total;
+			// save channel RF frequency
+			priv->global_channel_ts_table[cur_index].channel_freq_khz = Freq_Khz;
+			// save channel bandwidth
+			priv->global_channel_ts_table[cur_index].channel_bandwith_khz = BandWidth_Khz;
+			// save data plp id(not used for DVBT, set to 0xff)
+			priv->global_channel_ts_table[cur_index].data_plp_id = 0;
+			// 0 - DVBT; 1 - DVBT2.
+			priv->global_channel_ts_table[cur_index].channel_type = AVL_DVBTx_Standard_T;
+			// 0 - Low priority layer, 1 - High priority layer
+			priv->global_channel_ts_table[cur_index].dvbt_hierarchy_layer = 1;
+			cur_index++;
+
+			if(stDVBTxScanInfo.ucTxInfo == 1) {
+				// for hierarchy
+				// save channel RF frequency
+				priv->global_channel_ts_table[cur_index].channel_freq_khz = Freq_Khz;
+				// save channel bandwidth
+				priv->global_channel_ts_table[cur_index].channel_bandwith_khz = BandWidth_Khz;
+				// save data plp id(not used for DVBT, set to 0xff)
+				priv->global_channel_ts_table[cur_index].data_plp_id = 0;
+				// 0 - DVBT; 1 - DVBT2.
+				priv->global_channel_ts_table[cur_index].channel_type = AVL_DVBTx_Standard_T;
+				// 0 - Low priority layer, 1 - High priority layer
+				priv->global_channel_ts_table[cur_index].dvbt_hierarchy_layer = 0;
+				cur_index++;
+			}
+			priv->g_nChannel_ts_total = cur_index % MAX_CHANNEL_INFO;
+		}
+	} else {
+		// return for unlock
+		printk("[DVBTx_ScanChannel_Tx] DVBTx channel scan is fail,Err.\n");
+	}
+
+	/* lock channel */
+	for(i = 0; i < priv->g_nChannel_ts_total; i++) {
+		ucLockFlag = 0;
+	        if(priv->global_channel_ts_table[i].channel_type == AVL_DVBTx_Standard_T) {
+			//DVB-T signal..
+			AVL_LockChannel_T(priv, Freq_Khz, BandWidth_Khz, priv->global_channel_ts_table[i].dvbt_hierarchy_layer);
+		} else if (priv->global_channel_ts_table[i].channel_type == AVL_DVBTx_Standard_T2) {
+			//DVB-T2 signal, do not process FEF...
+			AVL_LockChannel_T2(priv, Freq_Khz, BandWidth_Khz,priv->global_channel_ts_table[i].channel_profile, priv->global_channel_ts_table[i].data_plp_id);
+		}
+		avl6882_demod_lock_wait(priv, &ucLockFlag);
+	}
+
+	return return_code;
+}
+
+
+
+
+int  AVL_Demod_DVBSx_Diseqc_SendTone(  struct avl6882_priv *priv,u8 ucTone, u8 ucCount)
+{
+	int r = 0;
+	u32 i1 = 0;
+	u32 i2 = 0;
+	//u8 pucBuffTemp[8] = {0};
+	u8 Continuousflag = 0;
+	u16 uiTempOutTh = 0;
+
+	if( ucCount>8 )
+	{
+		r = AVL_EC_WARNING;
+	}
+	else
+	{
+			if (priv->config->eDiseqcStatus == AVL_DOS_InContinuous)
+			{
+				r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+				if ((i1>>10) & 0x01)
+				{
+					Continuousflag = 1;
+					i1 &= 0xfffff3ff;
+					r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+					msleep(Diseqc_delay);		//delay 20ms
+				}
+			}
+			//No data in the FIFO.
+			r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+			i1 &= 0xfffffff8;  //put it into the FIFO load mode.
+			if( 0 == ucTone )
+			{
+				i1 |= 0x01;
+			}
+			else
+			{
+				i1 |= 0x02;
+			}
+			r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+
+			for (i2 = 0; i2 < ucCount; i2++) {
+				r |= AVL6882_WR_REG32(priv, 0x16c000 + hw_tx_fifo_map_offset, 1);
+			}
+#if 0
+			//trunk address
+			ChunkAddr_Demod(0x16c000 + hw_tx_fifo_map_offset, pucBuffTemp);
+			pucBuffTemp[3] = 0;
+			pucBuffTemp[4] = 0;
+			pucBuffTemp[5] = 0;
+			pucBuffTemp[6] = 1;
+
+			for( i2=0; i2<ucCount; i2++ )
+			{
+				r |= II2C_Write_Demod(priv, pucBuffTemp, 7);
+			}
+#endif
+
+			i1 |= (1<<2);  //start fifo transmit.
+			r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+			if( AVL_EC_OK == r )
+			{
+				priv->config->eDiseqcStatus = AVL_DOS_InTone;
+			}
+			do 
+			{
+				msleep(1);
+				if (++uiTempOutTh > 500)
+				{
+					r |= AVL_EC_TIMEOUT;
+					return(r);
+				}
+				r = AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_st_offset, &i1);
+			} while ( 1 != ((i1 & 0x00000040) >> 6) );
+
+			msleep(Diseqc_delay);		//delay 20ms
+			if (Continuousflag == 1)			//resume to send out wave
+			{
+				//No data in FIFO
+				r |= AVL6882_RD_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, &i1);
+				i1 &= 0xfffffff8; 
+				i1 |= 0x03; 	//switch to continuous mode
+				r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+				//start to send out wave
+				i1 |= (1<<10);	
+				r |= AVL6882_WR_REG32(priv,0x16c000 + hw_diseqc_tx_cntrl_offset, i1);
+
+			}
+		}
+	return (r);
+}
+
+
+
+
+
+#endif
+
+
+
+
+#if 0
+
+
+
+
+
+
+
+int  AVL_Demod_DVBSxManualLock( struct avl6882_priv *priv,AVL_DVBSxManualLockInfo *pstManualLockInfo)
+{
+	int r = AVL_EC_OK;
+	AVL_FunctionalMode eFuncMode = AVL_FuncMode_BlindScan;
+
+
+	r = AVL_Demod_DVBSx_GetFunctionalMode(priv,&eFuncMode);
+	if(eFuncMode == AVL_FuncMode_Demod)
+	{
+		r |= AVL6882_WR_REG16(priv,0xc00 + rs_DVBSx_fec_lock_saddr_offset, 0);	   
+
+		r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_fec_bypass_coderate_saddr_offset, 1);//DVBS manual lock
+
+		if (pstManualLockInfo->eDVBSxStandard == AVL_DVBS )
+		{
+			r |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_dvbs_fec_coderate_iaddr_offset, pstManualLockInfo->eDVBSCodeRate);
+		}
+		else if(pstManualLockInfo->eDVBSxStandard == AVL_DVBS2 )
+		{
+			r |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_dvbs2_code_rate_saddr_offset, pstManualLockInfo->eDVBS2CodeRate);
+			r |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_dvbs2_modulation_saddr_offset, pstManualLockInfo->eDVBSxModulationMode);
+		}
+		else
+		{
+			return AVL_EC_NOT_SUPPORTED;
+		}
+		r |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_decode_mode_saddr_offset, pstManualLockInfo->eDVBSxStandard);
+
+		if(pstManualLockInfo->eDVBSxSpecInversion == AVL_SPECTRUM_AUTO)
+		{
+			r |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_iq_mode_saddr_offset, 1);//enable spectrum auto detection
+		}
+		else
+		{
+			r |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_specinv_iaddr_offset, pstManualLockInfo->eDVBSxSpecInversion);
+			r |= AVL6882_WR_REG16(priv, 0xe00 + rc_DVBSx_iq_mode_saddr_offset, 0);
+		}
+
+		r |= AVL6882_WR_REG32(priv, 0xe00 + rc_DVBSx_int_sym_rate_MHz_iaddr_offset, pstManualLockInfo->uiDVBSxSymbolRateSps);
+
+		r |= avl6882_exec_n_wait(priv,AVL_FW_CMD_ACQUIRE );
+	}
+	else if(eFuncMode == AVL_FuncMode_BlindScan)
+	{
+		return AVL_EC_NOT_SUPPORTED;
+	}
+
+	return (r);
+}
+int  AVL_Demod_DVBSxGetModulationInfo( struct avl6882_priv *priv,AVL_DVBSxModulationInfo *pstModulationInfo)
+{
+	int r = AVL_EC_OK;
+	u32 uiTemp = 0;
+	u32  temp_uchar = 0;
+
+	r = AVL6882_RD_REG32(priv, 0xc00 + rs_DVBSx_pilot_iaddr_offset, &uiTemp);
+	pstModulationInfo->eDVBSxPilot = (AVL_DVBSx_Pilot)(uiTemp);
+
+	r |= AVL6882_RD_REG32(priv, 0xe00 + rc_DVBSx_internal_decode_mode_iaddr_offset,&uiTemp);
+	pstModulationInfo->eDVBSxStandard = (AVL_DVBSx_Standard)uiTemp;
+
+	if(AVL_DVBS == (AVL_DVBSx_Standard)uiTemp)
+	{
+		r |= AVL6882_RD_REG32(priv, 0xe00 + rc_DVBSx_dvbs_fec_coderate_iaddr_offset,&uiTemp);
+		pstModulationInfo->eDVBSCodeRate = (AVL_DVBS_CodeRate)(uiTemp);
+	}
+	else
+	{
+		r |= AVL6882_RD_REG8(priv, 0xe00 + rc_DVBSx_dvbs2_fec_coderate_caddr_offset,&temp_uchar);
+		pstModulationInfo->eDVBS2CodeRate = (AVL_DVBS2_CodeRate)(temp_uchar);
+	}
+
+	r |= AVL6882_RD_REG32(priv, 0xc00 + rs_DVBSx_modulation_iaddr_offset, &uiTemp);
+	pstModulationInfo->eDVBSxModulationMode = (AVL_DVBSx_ModulationMode)(uiTemp);
+
+	r |= AVL6882_RD_REG32(priv, 0xc00 + rs_DVBSx_detected_alpha_iaddr_offset, &uiTemp);
+	pstModulationInfo->eDVBSxRollOff = (AVL_DVBSx_RollOff)(uiTemp);
+
+	return (r);
+
+}
+
+int  AVL_Demod_DVBSx_BlindScan_Start( struct avl6882_priv *priv,AVL_BlindScanPara * pBSPara, u16 uiTunerLPF_100kHz)
+{
+	int r = AVL_EC_OK;
+	u16 uiCarrierFreq_100kHz = 0;
+	u16 uiMinSymRate = 0;
+	AVL_FunctionalMode enumFunctionalMode = AVL_FuncMode_Demod;
+
+	r = AVL_Demod_DVBSx_GetFunctionalMode(priv,&enumFunctionalMode);
+
+	if (enumFunctionalMode == AVL_FuncMode_BlindScan) {
+		r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_tuner_LPF_100kHz_saddr_offset, uiTunerLPF_100kHz);
+		r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_blind_scan_tuner_spectrum_inversion_saddr_offset, pBSPara->m_enumBSSpectrumPolarity);
+
+		uiMinSymRate = pBSPara->m_uiMinSymRate_kHz - 200;		// give some tolerance
+
+		if (uiMinSymRate < 800) 	  //Blind scan doesn't support symbol rate less then 1M, give 200K margin
+		{
+			uiMinSymRate = 800;
+		}
+
+		if( pBSPara->m_uiStartFreq_100kHz < pBSPara->m_uiStopFreq_100kHz )
+		{
+			if( AVL_EC_OK == r )
+			{
+				uiCarrierFreq_100kHz = ((pBSPara->m_uiStopFreq_100kHz)+(pBSPara->m_uiStartFreq_100kHz))>>1;
+				r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_tuner_frequency_100kHz_saddr_offset, uiCarrierFreq_100kHz);
+				r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_blind_scan_min_sym_rate_kHz_saddr_offset, uiMinSymRate);
+				r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_blind_scan_max_sym_rate_kHz_saddr_offset, (pBSPara->m_uiMaxSymRate_kHz)+200);
+				r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_blind_scan_start_freq_100kHz_saddr_offset, (pBSPara->m_uiStartFreq_100kHz));
+				r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_blind_scan_end_freq_100kHz_saddr_offset, (pBSPara->m_uiStopFreq_100kHz));
+
+				if( AVL_EC_OK == r )
+				{
+					r = avl6882_exec_n_wait(priv,AVL_FW_CMD_BLIND_SCAN);
+				}
+			}
+		}
+		else
+		{
+			r = AVL_EC_GENERAL_FAIL;
+		}
+	}
+	else
+	{
+		r = AVL_EC_GENERAL_FAIL;
+	}
+
+	return (r);
+}
+#endif
+
+#if 0
+// need fix read data size
+int  AVL_Demod_DVBSx_BlindScan_GetStatus( struct avl6882_priv *priv,AVL_BSInfo * pBSInfo)
+{
+	int r = AVL_EC_OK;
+
+	r = AVL6882_RD_REG16(priv,0xc00 + rs_DVBSx_blind_scan_progress_saddr_offset, &(pBSInfo->m_uiProgress));
+	r |= AVL6882_RD_REG16(priv,0xc00 + rs_DVBSx_blind_scan_channel_count_saddr_offset, &(pBSInfo->m_uiChannelCount));
+	r |= AVL6882_RD_REG16(priv,0xe00 + rc_DVBSx_blind_scan_start_freq_100kHz_saddr_offset, &(pBSInfo->m_uiNextStartFreq_100kHz));
+	r |= AVL6882_RD_REG16(priv,0xc00 + rs_DVBSx_blind_scan_error_code_saddr_offset, &(pBSInfo->m_uiResultCode));
+	if( pBSInfo->m_uiProgress > 100 )
+	{
+		pBSInfo->m_uiProgress = 0;
+	}
+
+	return(r);
+}
+
+int  AVL_Demod_DVBSx_BlindScan_Cancel( struct avl6882_priv *priv )
+{
+	int r;
+	enum AVL_FunctionalMode enumFunctionalMode = AVL_FuncMode_Demod;
+
+
+
+	r = AVL_Demod_DVBSx_GetFunctionalMode(priv,&enumFunctionalMode);
+
+	if(enumFunctionalMode == AVL_FuncMode_BlindScan)
+	{
+		r |= avl6882_exec_n_wait(priv,AVL_FW_CMD_HALT);
+	}
+	else
+	{
+		r = AVL_EC_GENERAL_FAIL;
+	}
+
+	return(r);
+}
+
+
+int  AVL_Demod_DVBSx_BlindScan_ReadChannelInfo( struct avl6882_priv *priv,u16 uiStartIndex, AVL_puint16 pChannelCount, AVL_ChannelInfo * pChannel)
+{
+	int r = 0;
+	u32 channel_addr = 0;
+	u16 i1 = 0;
+	u16 i2 = 0;
+	u32 uiMinFreq = 0;
+	u16 iMinIdx = 0;
+	AVL_ChannelInfo sTempChannel;
+
+
+
+	r = AVL6882_RD_REG16(priv,0xc00 + rs_DVBSx_blind_scan_channel_count_saddr_offset, &i1);
+	if( (uiStartIndex + (*pChannelCount)) > (i1) )
+	{
+		*pChannelCount = i1-uiStartIndex;
+	}
+	r |= AVL6882_RD_REG16(priv,0xe00 + rc_DVBSx_blind_scan_channel_info_offset_saddr_offset, &i1);
+	channel_addr = 0x200C00 + uiStartIndex*sizeof(AVL_ChannelInfo);
+	for( i1=0; i1<(*pChannelCount); i1++ )
+	{
+#if 1  //for some processors which can not read 12 bytes        
+		//dump the channel information
+		r |= AVL6882_RD_REG32(priv, channel_addr, &(pChannel[i1].m_uiFrequency_kHz));
+		channel_addr += 4;
+		r |= AVL6882_RD_REG32(priv, channel_addr, &(pChannel[i1].m_uiSymbolRate_Hz));
+		channel_addr += 4;
+		r |= AVL6882_RD_REG32(priv, channel_addr, &(pChannel[i1].m_Flags));
+		channel_addr += 4;
+#endif
+	}
+
+	// Sort the results
+	for(i1=0; i1<(*pChannelCount); i1++)
+	{
+		iMinIdx = i1;
+		uiMinFreq = pChannel[i1].m_uiFrequency_kHz;
+		for(i2=(i1+1); i2<(*pChannelCount); i2++)
+		{
+			if(pChannel[i2].m_uiFrequency_kHz < uiMinFreq)
+			{
+				uiMinFreq = pChannel[i2].m_uiFrequency_kHz;
+				iMinIdx = i2;
+			}
+		}
+		sTempChannel = pChannel[iMinIdx];
+		pChannel[iMinIdx] = pChannel[i1];
+		pChannel[i1] = sTempChannel;
+	}
+
+	return(r);
+}
+
+
+int  AVL_Demod_DVBSx_BlindScan_Reset( struct avl6882_priv *priv )
+{
+	return AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_blind_scan_reset_saddr_offset, 1);
+}
+
+
+int  AVL_Demod_DVBSx_SetFunctionalMode( struct avl6882_priv *priv,AVL_FunctionalMode enumFunctionalMode )
+{
+	int r = AVL_EC_OK;
+	r = AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_functional_mode_saddr_offset, (u16)enumFunctionalMode);
+	r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_iq_mode_saddr_offset,0);
+	return(r);
+}
+
+int  AVL_Demod_DVBSx_SetDishPointingMode(  struct avl6882_priv *priv,AVL_Switch enumOn_Off)
+{
+	int r = AVL_EC_OK;
+	AVL_FunctionalMode enumFunctionalMode = AVL_FuncMode_BlindScan;
+
+	r |= AVL_Demod_DVBSx_GetFunctionalMode(priv,&enumFunctionalMode);
+	if(enumFunctionalMode == AVL_FuncMode_Demod)
+	{
+		if(enumOn_Off == AVL_ON)
+		{
+			r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_aagc_acq_gain_saddr_offset, 12);
+			r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_dishpoint_mode_saddr_offset, 1);
+		}
+		else
+		{
+			r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_aagc_acq_gain_saddr_offset, 10);
+			r |= AVL6882_WR_REG16(priv,0xe00 + rc_DVBSx_dishpoint_mode_saddr_offset, 0);
+		}
+	}
+	else
+	{
+		r = AVL_EC_GENERAL_FAIL;
+	}
+
+	return(r);
+}
+#endif
+
+
+
+
+
+
+
+int  AVL_Demod_GetGPIOValue( struct avl6882_priv *priv, u8 ePinNumber, u8 *pePinValue)
+{
+	int r = AVL_EC_OK;
+
+
+	switch(ePinNumber)
+	{
+	case AVL_Pin37:
+		r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_0_sel_offset, GPIO_Z);
+		r = AVL6882_RD_REG32(priv,REG_GPIO_BASE + lnb_cntrl_0_i_offset, (AVL_puint32)pePinValue);
+		break;
+
+	case AVL_Pin38:
+		r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_1_sel_offset, GPIO_Z);
+		r = AVL6882_RD_REG32(priv,REG_GPIO_BASE + lnb_cntrl_1_i_offset, (AVL_puint32)pePinValue);
+		break;
+	default:
+		break;
+	}
+
+	return r;
+}
+
+
+
+int  AVL_Demod_SetGPIO( struct avl6882_priv *priv,u8 ePinNumber, u8 ePinValue)
+{
+	int r = AVL_EC_OK;
+
+	switch (ePinNumber) {
+	case AVL_Pin37:
+		r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_0_sel_offset, GPIO_0);
+
+		switch(ePinValue)
+		{
+		case GPIO_0:
+			r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_0_sel_offset, ePinValue);
+			break;
+		case GPIO_1:
+			r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_0_sel_offset, ePinValue);
+			break;
+		case GPIO_Z:
+			r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_0_sel_offset, ePinValue);
+			break;
+		default:
+			break;
+		}
+		break;
+	case AVL_Pin38:
+		r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_1_sel_offset, GPIO_0);
+
+		switch(ePinValue)
+		{
+		case GPIO_0:
+			r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_1_sel_offset, ePinValue);
+			break;
+		case GPIO_1:
+			r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_1_sel_offset, ePinValue);
+			break;
+		case GPIO_Z:
+			r = AVL6882_WR_REG32(priv,REG_GPIO_BASE + lnb_cntrl_1_sel_offset, ePinValue);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+	return r;
+}
+
+
+
+
+
+
+
+#if 0
+int  AVL_Demod_GetVersion( struct avl6882_priv *priv,AVL_DemodVersion *pstDemodVersion)
+{
+	int r = AVL_EC_OK;
+	u32 uiTemp = 0;
+	u8 ucBuff[4] = {0};
+
+	r =  AVL6882_RD_REG32(priv,0x40000, &uiTemp);
+	if( AVL_EC_OK == r )
+	{
+		pstDemodVersion->uiChip = uiTemp;
+	}
+
+	r |=  AVL6882_RD_REG32(priv,0x0a4 + rs_patch_ver_iaddr_offset, &uiTemp);
+	if( AVL_EC_OK == r )
+	{
+		Chunk32_Demod(uiTemp, ucBuff);
+		pstDemodVersion->stPatch.ucMajor = ucBuff[0];
+		pstDemodVersion->stPatch.ucMinor = ucBuff[1];
+		pstDemodVersion->stPatch.usBuild = ucBuff[2];
+		pstDemodVersion->stPatch.usBuild = ((u16)((pstDemodVersion->stPatch.usBuild)<<8)) + ucBuff[3];
+	}
+
+	return r;
+}
+#endif
+
+
+
+
+
+
+
+
+
diff -rpuN a/drivers/media/dvb/frontends/avl6882.h b/drivers/media/dvb/frontends/avl6882.h
--- a/drivers/media/dvb/frontends/avl6882.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/frontends/avl6882.h	2016-04-09 10:31:21.244008001 -0300
@@ -0,0 +1,58 @@
+/*
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+*/
+
+#ifndef AVL6882_H
+#define AVL6882_H
+
+//#include <linux/dvb/frontend.h>
+//#include "dvb_frontend.h"
+
+
+
+
+
+
+
+
+
+struct avl6882_config {
+	/* the demodulator's i2c address */
+	u8 demod_address;
+	u8 tuner_address;
+
+	unsigned char eDiseqcStatus;
+
+
+
+};
+
+
+#if defined(CONFIG_DVB_AVL6882) || (defined(CONFIG_DVB_AVL6882_MODULE) && \
+							defined(MODULE))
+extern struct dvb_frontend *avl6882_attach(struct avl6882_config *config,
+					   struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend *avl6882_attach(struct avl6882_config *config,
+					   struct i2c_adapter *i2c)
+{
+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+	return NULL;
+}
+#endif /* CONFIG_DVB_AVL6882 */
+
+#endif /* AVL6882_H */
diff -rpuN a/drivers/media/dvb/frontends/avl6882_priv.h b/drivers/media/dvb/frontends/avl6882_priv.h
--- a/drivers/media/dvb/frontends/avl6882_priv.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/frontends/avl6882_priv.h	2016-04-09 10:31:21.244008001 -0300
@@ -0,0 +1,1761 @@
+#ifndef AVL6882_PRIV_H
+#define AVL6882_PRIV_H
+
+#include "dvb_frontend.h"
+
+
+#define MAX_CHANNEL_INFO 256
+
+typedef struct s_DVBTx_Channel_TS
+{
+    // number, example 474*1000 is RF frequency 474MHz.
+    int channel_freq_khz;
+    // number, example 8000 is 8MHz bandwith channel.
+    int channel_bandwith_khz;
+
+    u8 channel_type;
+    // 0 - Low priority layer, 1 - High priority layer
+    u8 dvbt_hierarchy_layer;
+    // data PLP id, 0 to 255; for single PLP DVBT2 channel, this ID is 0; for DVBT channel, this ID isn't used.
+    u8 data_plp_id;
+    u8 channel_profile;
+}s_DVBTx_Channel_TS;
+
+
+
+struct avl6882_priv {
+	struct i2c_adapter *i2c;
+ 	struct avl6882_config *config;
+	struct dvb_frontend frontend;
+	enum fe_delivery_system delivery_system;
+
+	/* DVB-Tx */
+	u16 g_nChannel_ts_total;
+	s_DVBTx_Channel_TS global_channel_ts_table[MAX_CHANNEL_INFO];
+};
+
+
+
+
+
+typedef  int AVL_int32;     ///< 32 bits signed char data type.
+typedef  unsigned char * AVL_puchar; ///< pointer to a 8 bits unsigned char data type.
+typedef  unsigned short * AVL_puint16;  ///< pointer to a 16 bits unsigned char data type.
+typedef  unsigned int * AVL_puint32; ///< pointer to a 32 bits unsigned char data type.
+typedef unsigned char AVL_semaphore;    ///< the semaphore data type.
+
+
+
+
+
+
+/* known registers */
+
+/* TS */
+#define REG_TS_OUTPUT			(0x130420)
+#define TS_OUTPUT_ENABLE		(0)
+#define TS_OUTPUT_DISABLE		(0xfff)
+
+
+/* GPIO */
+#define REG_GPIO_BASE			(0x120000)
+
+#define GPIO_AGC_DVBTC			(0x00)	/* agc1_sel*/
+#define GPIO_AGC_DVBS			(0x10)	/* agc2_sel*/
+#define GPIO_LNB_VOLTAGE		(0x08)	/* pin 38 - lnb_ctrl_1_sel */
+#define GPIO_LNB_PWR			(0x0c)	/* pin 37 - lnb_ctrl_0_sel */
+
+#define GPIO_RD_MASK			(0x40)
+
+#define GPIO_0				(0)
+#define GPIO_1				(1)
+#define GPIO_Z				(2)
+#define GPIO_AGC_ON			(6)
+
+
+
+//GPIO control
+#define lnb_cntrl_1_sel_offset                   0x08 
+#define lnb_cntrl_0_sel_offset                   0x0c 
+
+#define lnb_cntrl_1_i_offset                     0x48
+#define lnb_cntrl_0_i_offset                     0x4c
+
+
+typedef enum AVL_GPIOPinNumber
+{
+    AVL_Pin37 = 0,
+    AVL_Pin38 = 1
+}AVL_GPIOPinNumber;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#define MAX_II2C_READ_SIZE  64
+#define MAX_II2C_WRITE_SIZE 64
+
+
+//SDK Version
+#define AVL_API_VER_MAJOR                   0x02
+#define AVL_API_VER_MINOR                   0x03
+#define AVL_API_VER_BUILD                   0x02
+
+
+#define AVL68XX                            0x68624955
+
+#define AVL_FW_CMD_IDLE                          0
+#define AVL_FW_CMD_LD_DEFAULT                    1
+#define AVL_FW_CMD_ACQUIRE                       2
+#define AVL_FW_CMD_HALT                          3 
+#define AVL_FW_CMD_DEBUG                         4
+#define AVL_FW_CMD_SLEEP                         7
+#define AVL_FW_CMD_WAKE                          8
+#define AVL_FW_CMD_BLIND_SCAN                    9
+#define AVL_FW_CMD_SDRAM_TEST                   16
+#define AVL_FW_CMD_INIT_SDRAM                   17
+#define AVL_FW_CMD_INIT_ADC                     18
+#define AVL_FW_CMD_CHANGE_MODE                  19
+
+#define AVL_FW_CMD_DMA                          21
+#define AVL_FW_CMD_CALC_CRC                     22
+#define AVL_FW_CMD_PING                         23
+#define AVL_FW_CMD_DECOMPRESS                   24
+
+
+
+/*
+ * Patch file stuff
+ */
+#define PATCH_VAR_ARRAY_SIZE                32
+
+#define PATCH_CMD_VALIDATE_CRC              0
+#define PATCH_CMD_PING                      1 
+#define PATCH_CMD_LD_TO_DEVICE              2 
+#define PATCH_CMD_DMA                       3 
+#define PATCH_CMD_DECOMPRESS                4
+#define PATCH_CMD_ASSERT_CPU_RESET          5 
+#define PATCH_CMD_RELEASE_CPU_RESET         6
+#define PATCH_CMD_LD_TO_DEVICE_IMM          7
+#define PATCH_CMD_RD_FROM_DEVICE            8
+#define PATCH_CMD_DMA_HW                    9
+#define PATCH_CMD_SET_COND_IMM              10
+#define PATCH_CMD_EXIT                      11
+
+
+#define PATCH_CMP_TYPE_ZLIB                 0
+#define PATCH_CMP_TYPE_ZLIB_NULL            1
+#define PATCH_CMP_TYPE_GLIB                 2
+#define PATCH_CMP_TYPE_NONE                 3
+
+//Addr modes 2 bits
+#define PATCH_OP_ADDR_MODE_VAR_IDX          0
+#define PATCH_OP_ADDR_MODE_IMMIDIATE        1
+
+//Unary operators 6 bits
+#define PATCH_OP_UNARY_NOP                  0
+#define PATCH_OP_UNARY_LOGICAL_NEGATE       1
+#define PATCH_OP_UNARY_BITWISE_NEGATE       2
+#define PATCH_OP_UNARY_BITWISE_AND          3
+#define PATCH_OP_UNARY_BITWISE_OR           4
+
+//Binary operators 1 Byte
+#define PATCH_OP_BINARY_LOAD                0
+#define PATCH_OP_BINARY_AND                 1
+#define PATCH_OP_BINARY_OR                  2
+#define PATCH_OP_BINARY_BITWISE_AND         3
+#define PATCH_OP_BINARY_BITWISE_OR          4
+#define PATCH_OP_BINARY_EQUALS              5
+#define PATCH_OP_BINARY_STORE               6
+#define PATCH_OP_BINARY_NOT_EQUALS          7
+
+#define PATCH_COND_EXIT_AFTER_LD            8
+
+#define PATCH_STD_DVBC                      0 
+#define PATCH_STD_DVBSx                     1
+#define PATCH_STD_DVBTx                     2
+#define PATCH_STD_ISDBT                     3
+
+
+
+#define tuner_i2c_srst_offset                0x0
+#define tuner_i2c_cntrl_offset               0x4
+#define tuner_i2c_bit_rpt_clk_div_offset     0x18
+#define tuner_i2c_bit_rpt_cntrl_offset       0x1C
+
+#define esm_cntrl_offset                    0x4
+#define bit_error_offset                    0x8
+#define byte_num_offset                     0xC
+#define packet_error_offset                 0x10
+#define packet_num_offset                   0x14
+#define tick_clear_offset                   0x88
+#define tick_type_offset                    0x8C
+#define time_tick_low_offset                0x90
+#define time_tick_high_offset               0x94
+#define byte_tick_low_offset                0x98
+#define byte_tick_high_offset               0x9C
+#define esm_mode_offset                     0xC0
+
+#define rs_current_active_mode_iaddr_offset 0x24
+#define rc_fw_command_saddr_offset          0x00
+#define rs_core_ready_word_iaddr_offset     0xa0
+#define rc_sdram_test_return_iaddr_offset   0x3C
+#define rc_sdram_test_result_iaddr_offset   0x40
+#define rs_rf_agc_saddr_offset              0x44
+
+#define rc_fw_command_args_addr_iaddr_offset 0x58
+
+#define rc_ts_cntns_clk_frac_d_iaddr_offset                 0x0000007c
+#define rc_ts_cntns_clk_frac_n_iaddr_offset                 0x00000078
+#define rc_enable_ts_continuous_caddr_offset                0x0000003a
+#define rc_ts_clock_edge_caddr_offset                       0x0000003b
+#define rc_ts_serial_caddr_offset                           0x0000003c
+#define rc_ts_serial_outpin_caddr_offset                    0x0000003f
+#define rc_ts_serial_msb_caddr_offset                       0x0000003e
+#define rc_ts_packet_len_caddr_offset                       0x00000039
+#define rc_ts_packet_order_caddr_offset                     rc_ts_serial_msb_caddr_offset
+#define rc_ts_error_bit_en_caddr_offset                     0x000000000
+#define rc_ts_error_polarity_caddr_offset                   0x00000041
+#define rc_ts_valid_polarity_caddr_offset                   0x00000040
+#define rc_ts_sync_pulse_caddr_offset                       0x00000097
+#define ts_clock_phase_caddr_offset                         0x00000096
+
+#define rs_patch_ver_iaddr_offset           0x00000004
+
+
+
+
+#define hw_AVL_rx_rf_aagc_gain              0x160888
+
+
+//Define ADC channel selection
+typedef enum AVL_ADC_Channel
+{
+    AVL_ADC_CHAN2   =   0,
+    AVL_ADC_CHAN1   =   1,
+    AVL_ADC_OFF     =   2
+}AVL_ADC_Channel;
+
+typedef enum AVL_ADC_Output_format
+{
+    AVL_2COMP    =   0,
+    AVL_OFFBIN   =   1
+}AVL_ADC_Output_format;
+
+//Input_select enumeration definitions
+typedef enum AVL_DDC_Input
+{
+    AVL_DIG_IN       =   0,
+    AVL_ADC_IN       =   1,
+    AVL_VEC_IN       =   2,
+    AVL_VEC1x_IN     =   3,
+    AVL_DIG1x_IN     =   4
+}AVL_DDC_Input;
+
+// Defines BER type
+typedef enum AVL_BER_Type
+{
+    AVL_PRE_VITERBI_BER     =   0,                      // previous viterbi BER will be acquired.
+    AVL_POST_VITERBI_BER    =   1,                      // post viterbi BER will be acquired.
+    AVL_PRE_LDPC_BER        =   2,                      // previous LDPC BER will be acquired.
+    AVL_POST_LDPC_BER       =   3,                      // post LDPC BER will be acquired.
+    AVL_FINAL_BER           =   4                       // final BER will be acquired.
+}AVL_BER_Type;
+
+// Defines different standards supported by the demod.
+typedef enum AVL_DemodMode
+{
+    AVL_DVBC = 0,
+    AVL_DVBSX = 1,
+    AVL_DVBTX = 2,
+    AVL_ISDBT = 3,
+    AVL_DTMB = 4,
+    AVL_ISDBS = 5,
+    AVL_ABSS = 6,
+    AVL_ATSC = 7,
+    AVL_DVBC2 = 8
+} AVL_DemodMode;
+
+// Defines the channel lock mode.
+typedef enum AVL_LockMode
+{
+    AVL_LOCK_MODE_AUTO      =   0,                      // lock channel automatically.
+    AVL_LOCK_MODE_MANUAL    =   1                       // lock channel manually.
+}AVL_LockMode;
+
+// Defines channel lock status
+typedef enum AVL_LockStatus
+{
+    AVL_STATUS_UNLOCK   =   0,                          // channel isn't locked
+    AVL_STATUS_LOCK     =   1                           // channel is in locked state.
+}AVL_LockStatus;
+
+typedef enum AVL_TSMode
+{
+    AVL_TS_PARALLEL = 0, 
+    AVL_TS_SERIAL =   1
+}AVL_TSMode; 
+
+typedef enum AVL_TSClockEdge
+{
+    AVL_MPCM_FALLING   =   0, 
+    AVL_MPCM_RISING    =   1  
+} AVL_TSClockEdge; 
+
+typedef enum AVL_TSClockMode
+{
+    AVL_TS_CONTINUOUS_ENABLE = 0,   
+    AVL_TS_CONTINUOUS_DISABLE = 1      
+} AVL_TSClockMode; 
+
+typedef enum AVL_TSSerialPin
+{
+    AVL_MPSP_DATA0  =   0, 
+    AVL_MPSP_DATA7  =   1  
+} AVL_TSSerialPin; 
+
+typedef enum AVL_TSSerialOrder
+{
+    AVL_MPBO_LSB = 0, 
+    AVL_MPBO_MSB = 1 
+} AVL_TSSerialOrder; 
+
+typedef enum AVL_TSSerialSyncPulse
+{
+    AVL_TS_SERIAL_SYNC_8_PULSE    =   0,         
+    AVL_TS_SERIAL_SYNC_1_PULSE      =   1        
+} AVL_TSSerialSyncPulse; 
+
+typedef enum AVL_TSErrorBit
+{
+    AVL_TS_ERROR_BIT_DISABLE  =   0,  
+    AVL_TS_ERROR_BIT_ENABLE   =   1  
+} AVL_TSErrorBit; 
+
+typedef enum AVL_TSErrorPolarity
+{
+    AVL_MPEP_Normal = 0,  
+    AVL_MPEP_Invert = 1  
+} AVL_TSErrorPolarity; 
+
+typedef enum AVL_TSValidPolarity
+{
+    AVL_MPVP_Normal     =   0, 
+    AVL_MPVP_Invert     =   1   
+} AVL_TSValidPolarity; 
+
+typedef enum AVL_TSPacketLen
+{
+    AVL_TS_188 = 0,
+    AVL_TS_204 = 1
+} AVL_TSPacketLen; 
+
+typedef enum AVL_AGCPola
+{
+    AVL_AGC_NORMAL  =   0,        //  normal AGC polarity. Used for a tuner whose gain increases with increased AGC voltage.
+    AVL_AGC_INVERTED=   1         //  inverted AGC polarity. Used for tuner whose gain decreases with increased AGC voltage.
+}AVL_AGCPola;
+
+typedef enum AVL_TSParallelOrder
+{
+    AVL_TS_PARALLEL_ORDER_INVERT =   0,
+    AVL_TS_PARALLEL_ORDER_NORMAL =   1
+} AVL_TSParallelOrder; 
+
+typedef enum AVL_TSParallelPhase
+{
+    AVL_TS_PARALLEL_PHASE_0 = 0,
+    AVL_TS_PARALLEL_PHASE_1 = 1,
+    AVL_TSG_PARALLEL_PHASE_2 = 2,
+    AVL_TS_PARALLEL_PHASE_3 = 3
+}AVL_TSParallelPhase;
+
+// Stores an unsigned 64-bit integer
+typedef struct AVLuint64
+{
+    u32 uiHighWord;                  // The most significant 32-bits of the unsigned 64-bit integer
+    u32 uiLowWord;                   // The least significant 32-bits of the unsigned 64-bit integer
+}AVLuint64;
+
+
+// Defines whether the feeback bit of the LFSR used to generate the BER/PER test pattern is inverted.
+typedef enum AVL_LFSR_FbBit
+{
+    AVL_LFSR_FB_NOT_INVERTED    =   0,          // LFSR feedback bit isn't inverted
+    AVL_LFSR_FB_INVERTED        =   1           // LFSR feedback bit is inverted
+}AVL_LFSR_FbBit;
+
+// Defines the test pattern being used for BER/PER measurements.
+typedef enum AVL_TestPattern
+{
+    AVL_TEST_LFSR_15    =   0,                  // BER test pattern is LFSR15
+    AVL_TEST_LFSR_23    =   1                   // BER test pattern is LFSR23        
+}AVL_TestPattern;
+
+// Defines the type of auto error statistics 
+typedef enum AVL_AutoErrorStat_Type
+{
+    AVL_ERROR_STAT_BYTE     =   0,                      // error statistics will be reset according to the number of received bytes.
+    AVL_ERROR_STAT_TIME     =   1                       // error statistics will be reset according to time interval.
+}AVL_AutoErrorStat_Type;
+
+// Defines Error statistics mode
+typedef enum AVL_ErrorStat_Mode
+{
+    AVL_ERROR_STAT_MANUAL   =   0,
+    AVL_ERROR_STAT_AUTO     =   1
+}AVL_ErrorStat_Mode;
+
+//Emerald2  PLL
+#define hw_E2_AVLEM61_reset_register                       0x00100000
+#define hw_E2_AVLEM61_dll_init                             0x00100008
+#define hw_E2_AVLEM61_deglitch_mode                        0x00100010
+#define hw_E2_AVLEM61_sys_pll_bypass                       0x00100040
+#define hw_E2_AVLEM61_sys_pll_enable                       0x00100044
+#define hw_E2_AVLEM61_sys_pll_divr                         0x00100048
+#define hw_E2_AVLEM61_sys_pll_divf                         0x0010004c
+#define hw_E2_AVLEM61_sys_pll_divq                         0x00100050
+#define hw_E2_AVLEM61_sys_pll_range                        0x00100054
+#define hw_E2_AVLEM61_sys_pll_lock                         0x00100058
+#define hw_E2_AVLEM61_mpeg_pll_bypass                      0x0010005c
+#define hw_E2_AVLEM61_mpeg_pll_enable                      0x00100060
+#define hw_E2_AVLEM61_mpeg_pll_divr                        0x00100064
+#define hw_E2_AVLEM61_mpeg_pll_divf                        0x00100068
+#define hw_E2_AVLEM61_mpeg_pll_divq                        0x0010006c
+#define hw_E2_AVLEM61_mpeg_pll_range                       0x00100070
+#define hw_E2_AVLEM61_mpeg_pll_lock                        0x00100074
+#define hw_E2_AVLEM61_adc_pll_bypass                       0x00100078 
+#define hw_E2_AVLEM61_adc_pll_enable                       0x0010007c
+#define hw_E2_AVLEM61_adc_pll_divr                         0x00100080
+#define hw_E2_AVLEM61_adc_pll_divf                         0x00100084
+#define hw_E2_AVLEM61_adc_pll_divq                         0x00100088
+#define hw_E2_AVLEM61_adc_pll_range                        0x0010008c
+#define hw_E2_AVLEM61_adc_pll_lock                         0x00100090
+#define hw_E2_AVLEM61_mpeg_pll_reset                       0x00100094
+#define hw_E2_AVLEM61_adc_pll_reset                        0x00100098
+#define hw_E2_AVLEM61_sys_pll_reset                        0x0010009c
+#define hw_E2_AVLEM61_sys_pll_enable2                      0x001000b4
+#define hw_E2_AVLEM61_sys_pll_enable3                      0x001000b8
+#define hw_E2_AVLEM61_sys_pll_divq2                        0x001000bc
+#define hw_E2_AVLEM61_sys_pll_divq3                        0x001000c0
+#define hw_E2_AVLEM61_mpeg_pll_enable2                     0x001000c4
+#define hw_E2_AVLEM61_mpeg_pll_enable3                     0x001000c8
+#define hw_E2_AVLEM61_mpeg_pll_divq2                       0x001000cc
+#define hw_E2_AVLEM61_mpeg_pll_divq3                       0x001000d0
+#define hw_E2_AVLEM61_adc_pll_enable2                      0x001000d4
+#define hw_E2_AVLEM61_adc_pll_enable3                      0x001000d8
+#define hw_E2_AVLEM61_adc_pll_divq2                        0x001000dc
+#define hw_E2_AVLEM61_adc_pll_divq3                        0x001000e0
+#define hw_E2_AVLEM61_ddc_clk_sel                          0x001000e4
+#define hw_E2_AVLEM61_sdram_clk_sel                        0x001000e8
+#define hw_E2_AVLEM61_dll_out_phase                        0x00000100
+#define hw_E2_AVLEM61_dll_rd_phase                         0x00000104
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// Defines the DiSEqC status
+typedef enum AVL_DiseqcStatus
+{
+    AVL_DOS_Uninitialized = 0,                  // DiSEqC has not been initialized yet.
+    AVL_DOS_Initialized   = 1,                  // DiSEqC has been initialized.
+    AVL_DOS_InContinuous  = 2,                  // DiSEqC is in continuous mode.
+    AVL_DOS_InTone        = 3,                  // DiSEqC is in tone burst mode.
+    AVL_DOS_InModulation  = 4                   // DiSEqC is in modulation mode.
+}AVL_DiseqcStatus;
+
+// Contains variables for storing error statistics used in the BER and PER calculations.
+typedef  struct AVL_ErrorStats
+{
+    u16 usLFSRSynced;    // Indicates whether the receiver is synchronized with the transmitter generating the BER test pattern.
+    u16 usLostLock;      // Indicates whether the receiver has lost lock since the BER/PER measurement was started.
+    AVLuint64 stSwCntNumBits;     // A software counter which stores the number of bits which have been received.
+    AVLuint64 stSwCntBitErrors;   // A software counter which stores the number of bit errors which have been detected.
+    AVLuint64 stNumBits;          // The total number of bits which have been received.
+    AVLuint64 stBitErrors;        // The total number of bit errors which have been detected.
+    AVLuint64 stSwCntNumPkts;     // A software counter which stores the number of packets which have been received.
+    AVLuint64 stSwCntPktErrors;   // A software counter which stores the number of packet errors which have been detected.
+    AVLuint64 stNumPkts;          // The total number of packets which have been received.
+    AVLuint64 stPktErrors;        // The total number of packet errors which have been detected.
+    u32 uiBER;             // The bit error rate scaled by 1e9.
+    u32 uiPER;             // The packet error rate scaled by 1e9.
+}AVL_ErrorStats;
+
+typedef enum AVL_Demod_Xtal
+{
+    Xtal_30M = 0,
+    Xtal_16M,
+    Xtal_24M,
+    Xtal_27M
+} AVL_Demod_Xtal;
+
+typedef enum AVL_InputPath
+{
+    AVL_IF_I,
+    AVL_IF_Q
+} AVL_InputPath;
+
+// Contains variables for storing error statistics used in the BER and PER calculations.
+typedef  struct AVL_ErrorStatConfig
+{
+    AVL_ErrorStat_Mode      eErrorStatMode;           // indicates the error statistics mode. 
+    AVL_AutoErrorStat_Type  eAutoErrorStatType;       // indicates the MPEG data sampling clock mode.
+    u32              uiTimeThresholdMs;        // used to set time interval for auto error statistics.
+    u32              uiNumberThresholdByte;    // used to set the received byte number threshold for auto error statistics.
+}AVL_ErrorStatConfig;
+
+// Contains variables for storing error statistics used in the BER and PER calculations.
+typedef  struct AVL_BERConfig
+{
+    AVL_TestPattern         eBERTestPattern;         // indicates the pattern of LFSR.
+    AVL_LFSR_FbBit          eBERFBInversion;         // indicates LFSR feedback bit inversion.
+    u32              uiLFSRSynced;                // indicates the LFSR synchronization status.
+    u32              uiLFSRStartPos;         //set LFSR start byte positon
+}AVL_BERConfig;
+
+
+
+
+/*
+typedef struct AVL_StandardSpecificFunctions
+{
+    AVL_Func_Initialize fpRxInitializeFunc;
+    AVL_Func_GetLockStatus fpGetLockStatus;
+    AVL_Func_GetSNR fpGetSNR;
+    AVL_Func_GetSQI fpGetSQI;
+    AVL_Func_GetPrePostBER fpGetPrePostBER;
+}AVL_StandardSpecificFunctions;
+*/
+typedef struct AVL_DVBTxPara
+{
+    AVL_InputPath eDVBTxInputPath;
+    u32 uiDVBTxIFFreqHz;
+    AVL_AGCPola eDVBTxAGCPola;
+} AVL_DVBTxPara;
+
+typedef enum AVL_Diseqc_WaveFormMode
+{
+    AVL_DWM_Normal = 0,                         // Normal waveform mode
+    AVL_DWM_Envelope = 1                        // Envelope waveform mode
+}AVL_Diseqc_WaveFormMode;
+
+typedef struct AVL_DVBSxPara
+{
+    AVL_semaphore semDiseqc;
+    AVL_DiseqcStatus eDiseqcStatus;
+    AVL_AGCPola eDVBSxAGCPola;
+    AVL_Diseqc_WaveFormMode e22KWaveForm;
+}AVL_DVBSxPara;
+
+typedef enum AVL_ISDBT_BandWidth
+{
+    AVL_ISDBT_BW_6M  =   0,
+    AVL_ISDBT_BW_8M  =   1,
+}AVL_ISDBT_BandWidth;
+
+typedef struct AVL_ISDBTPara
+{
+    AVL_InputPath eISDBTInputPath;
+    AVL_ISDBT_BandWidth eISDBTBandwidth;
+    u32 uiISDBTIFFreqHz;
+    AVL_AGCPola eISDBTAGCPola;
+} AVL_ISDBTPara;
+
+typedef struct AVL_DTMBPara
+{
+    AVL_InputPath eDTMBInputPath;
+    u32 uiDTMBIFFreqHz;
+    u32 uiDTMBSymbolRateHz;
+    AVL_AGCPola eDTMBAGCPola;
+} AVL_DTMBPara;
+
+typedef enum AVL_DVBC_Standard
+{
+    AVL_DVBC_J83A    =   0,           //the J83A standard
+    AVL_DVBC_J83B    =   1,           //the J83B standard
+    AVL_DVBC_UNKNOWN =   2
+}AVL_DVBC_Standard;
+
+typedef struct AVL_DVBCPara
+{
+    AVL_InputPath eDVBCInputPath;
+    u32 uiDVBCIFFreqHz;
+    u32 uiDVBCSymbolRateSps;
+    AVL_AGCPola eDVBCAGCPola;
+    AVL_DVBC_Standard eDVBCStandard;
+} AVL_DVBCPara;
+
+/**************************************************/
+typedef struct AVL_CommonConfig
+{
+    u16      usI2CAddr;
+    AVL_Demod_Xtal  eDemodXtal;
+    AVL_TSMode      eTSMode;
+    AVL_TSClockEdge eClockEdge;
+    AVL_TSClockMode eClockMode;
+}AVL_CommonConfig;
+
+typedef struct AVL_DVBTxConfig
+{
+    AVL_InputPath eDVBTxInputPath;
+    u32  uiDVBTxIFFreqHz;
+    AVL_AGCPola eDVBTxAGCPola;
+} AVL_DVBTxConfig;
+
+typedef struct AVL_DVBCConfig
+{ 
+    AVL_InputPath eDVBCInputPath;
+    u32 uiDVBCIFFreqHz;
+    u32 uiDVBCSymbolRateSps;
+    AVL_AGCPola eDVBCAGCPola;
+    AVL_DVBC_Standard eDVBCStandard;
+} AVL_DVBCConfig;
+
+typedef struct AVL_DVBSxConfig
+{
+    AVL_AGCPola eDVBSxAGCPola;
+    AVL_Diseqc_WaveFormMode e22KWaveForm;
+} AVL_DVBSxConfig;
+
+typedef struct AVL_DTMBConfig
+{
+    AVL_InputPath eDTMBInputPath;
+    u32 uiDTMBIFFreqHz;
+    u32 uiDTMBSymbolRateHz;
+    AVL_AGCPola eDTMBAGCPola;
+} AVL_DTMBConfig;
+
+typedef struct AVL_ISDBTConfig
+{ 
+    AVL_InputPath eISDBTInputPath;
+    AVL_ISDBT_BandWidth eISDBTBandwidth;
+    u32 uiISDBTIFFreqHz;
+    AVL_AGCPola eISDBTAGCPola;
+} AVL_ISDBTConfig;
+
+typedef struct AVL_TSConfig
+{
+    AVL_TSMode eMode;
+    AVL_TSClockEdge eClockEdge;
+    AVL_TSClockMode eClockMode;
+    AVL_TSSerialPin eSerialPin;
+    AVL_TSSerialOrder eSerialOrder;
+    AVL_TSSerialSyncPulse eSerialSyncPulse;
+    AVL_TSErrorBit eErrorBit;
+    AVL_TSErrorPolarity eErrorPolarity;
+    AVL_TSValidPolarity eValidPolarity;
+    AVL_TSPacketLen ePacketLen;
+    AVL_TSParallelOrder eParallelOrder;
+    u32 guiDVBTxSerialTSContinuousHz;
+    u32 guiDVBSxSerialTSContinuousHz;
+    u32 guiISDBTSerialTSContinuousHz;
+    u32 guiDTMBSerialTSContinuousHz;
+    u32 guiDVBCSerialTSContinuousHz;
+}AVL_TSConfig;
+
+typedef struct AVL_BaseAddressSet
+{
+    u32 hw_mcu_reset_base;
+    u32 hw_mcu_system_reset_base;
+    u32 hw_esm_base;
+    u32 hw_tuner_i2c_base;
+    u32 hw_gpio_control_base;
+    u32 hw_gpio_debug_base;
+    u32 hw_TS_tri_state_cntrl_base;
+    u32 hw_AGC_tri_state_cntrl_base;
+    u32 hw_diseqc_base;
+    u32 hw_plp_list_base;
+    u32 hw_blind_scan_info_base;
+    u32 hw_member_ID_base;
+    u32 hw_dma_sys_status_base;
+    u32 hw_dma_sys_cmd_base;
+    u32 fw_config_reg_base;
+    u32 fw_status_reg_base;
+    u32 fw_DVBTx_config_reg_base;
+    u32 fw_DVBTx_status_reg_base;
+    u32 fw_DVBT2_data_PLP_config_reg_base;
+    u32 fw_DVBT2_common_PLP_config_reg_base;
+    u32 fw_DVBT2_P1_reg_base;
+    u32 fw_DVBT2_L1_pre_reg_base;
+    u32 fw_DVBT2_L1_post_config_reg_base;
+    u32 fw_DVBT_TPS_reg_base;
+    u32 fw_DVBSx_config_reg_base;
+    u32 fw_DVBSx_status_reg_base;
+    u32 fw_ISDBT_config_reg_base;
+    u32 fw_ISDBT_status_reg_base;
+    u32 fw_DTMB_config_reg_base;
+    u32 fw_DTMB_status_reg_base;
+    u32 fw_DVBC_config_reg_base;
+    u32 fw_DVBC_status_reg_base;
+}AVL_BaseAddressSet;
+
+typedef struct AVL_ChipInternal
+{
+    u16 usI2CAddr;
+    u32 uiFamilyID;
+    AVL_Demod_Xtal eDemodXtal;
+    AVL_DemodMode eCurrentDemodMode;
+    AVL_semaphore semRx;
+    u32 uiCoreFrequencyHz;
+    u32 uiFECFrequencyHz;
+    u32 uiTSFrequencyHz;
+    u32 uiADCFrequencyHz;
+    u32 uiRefFrequencyHz;
+    u32 uiDDCFrequencyHz;
+    u32 uiSDRAMFrequencyHz;
+    AVL_TSConfig stTSConfig;
+    AVL_ErrorStatConfig stErrorStatConfig;
+    AVL_DVBTxPara stDVBTxPara;
+    AVL_DVBSxPara stDVBSxPara;
+    AVL_ISDBTPara stISDBTPara;
+    AVL_DTMBPara stDTMBPara;
+    AVL_DVBCPara stDVBCPara;
+//    AVL_StandardSpecificFunctions stStdSpecFunc;
+    u8 ucCustomizeFwData;
+    AVL_BaseAddressSet stBaseAddrSet;
+    AVL_ErrorStats stAVLErrorStat;
+    AVL_puchar DVBTxFwData;
+    AVL_puchar DVBSxFwData;
+    AVL_puchar ISDBTFwData;
+    AVL_puchar DVBCFwData;
+    AVL_puchar DTMBFwData;
+	u32 variable_array[PATCH_VAR_ARRAY_SIZE];
+
+    AVL_TSSerialPin eTSSerialPin;
+    AVL_TSSerialOrder eTSSerialOrder;
+    AVL_TSSerialSyncPulse eTSSerialSyncPulse;
+    AVL_TSErrorBit eTSErrorBit;
+    AVL_TSErrorPolarity eTSErrorPola;
+    AVL_TSValidPolarity eTSValidPola;
+    AVL_TSPacketLen eTSPacketLen;
+    AVL_TSParallelOrder eTSParallelOrder;
+    AVL_TSParallelPhase eTSParallelPhase;
+
+    u8 ucDisableTCAGC;
+    u8 ucDisableSAGC;
+    u8 ucDisableTSOutput;
+    
+    u8 ucPin37Status; // 0 - InPut; 1- OutPut
+    u8 ucPin38Status;
+    u8 ucPin37Voltage; // 0 - High; 1- Low; 2 - High_Z
+    u8 ucPin38Voltage;   
+
+    u8 ucSleepFlag;  //0 - Wakeup, 1 - Sleep 
+
+} AVL_ChipInternal;
+
+// The Availink version structure.
+typedef struct AVL_Version
+{
+    u8   ucMajor;                            // The major version number.
+    u8   ucMinor;                            // The minor version number.
+    u16  usBuild;                            // The build version number.
+}AVL_Version;
+
+// Stores AVLEM61 device version information.
+typedef struct AVL_DemodVersion
+{
+    u32  uiChip;                             // Hardware version information. 0xYYYYMMDD
+    AVL_Version stPatch;                            // The version of the internal patch.
+} AVL_DemodVersion;
+
+
+#define Diseqc_delay 20
+ 
+#define AVL_EC_OK                   0           // There is no error. 
+#define AVL_EC_WARNING              1           // There is warning. 
+#define AVL_EC_GENERAL_FAIL         2           // A general failure has occurred. 
+#define AVL_EC_I2C_FAIL             4           // An I2C operation failed during communication with the AVLEM61 through the BSP. 
+#define AVL_EC_I2C_REPEATER_FAIL    8           // An error ocurred during communication between AVLEM61 I2C master and tuner. This error code is defined by enum AVLEM61_MessageType_II2C_Repeater_Status.                        	 
+#define AVL_EC_RUNNING              16          // The AVLEM61 device is busy processing a previous receiver/i2c repeater command. 
+#define AVL_EC_TIMEOUT              32          // Operation failed in a given time period 
+#define AVL_EC_SLEEP                64          // Demod in sleep mode 
+#define AVL_EC_NOT_SUPPORTED        128         // Specified operation isn't support in current senario 
+#define AVL_EC_BSP_ERROR1           256         // BSP Error 1, if it's used, need to be customized 
+#define AVL_EC_BSP_ERROR2           512         // BSP Error 2, if it's used, need to be customized 
+ 
+#define AVL_CONSTANT_10_TO_THE_9TH      1000000000  //10e9 
+ 
+ 
+ 
+#define AVL_min(x,y) (((x) < (y)) ? (x) : (y)) 
+#define AVL_max(x,y) (((x) < (y)) ? (y) : (x)) 
+#define AVL_floor(a) (((a) == (int)(a))? ((int)(a)) : (((a) < 0)? ((int)((a)-1)) : ((int)(a)))) 
+#define AVL_ceil(a)  (((a) == (int)(a))? ((int)(a)) : (((a) < 0)? ((int)(a)) : ((int)((a)+1)))) 
+#define AVL_abs(a)  (((a)>0) ? (a) : (-(a))) 
+
+
+
+
+
+
+
+
+/* DVBS header file */
+#define rc_DVBSx_rfagc_pol_iaddr_offset                                  0x00000000
+#define rc_DVBSx_internal_decode_mode_iaddr_offset                        0x0000000c
+#define rc_DVBSx_format_iaddr_offset                                      0x00000010
+#define rc_DVBSx_input_iaddr_offset                                       0x00000014
+#define rc_DVBSx_specinv_iaddr_offset                                     0x00000034
+#define rc_DVBSx_dvbs_fec_coderate_iaddr_offset                           0x00000044
+#define rc_DVBSx_int_sym_rate_MHz_iaddr_offset                            0x00000054
+#define rc_DVBSx_aagc_acq_gain_saddr_offset                               0x000000fe
+#define rc_DVBSx_Max_LowIF_sps_iaddr_offset                               0x000000a4
+#define rc_DVBSx_int_dmd_clk_MHz_saddr_offset                             0x00000164
+#define rc_DVBSx_int_mpeg_clk_MHz_saddr_offset                            0x00000168
+#define rc_DVBSx_int_fec_clk_MHz_saddr_offset                             0x0000016a
+#define rc_DVBSx_fec_bypass_coderate_saddr_offset                         0x0000019a
+#define rc_DVBSx_tuner_frequency_100kHz_saddr_offset                      0x000001c0
+#define rc_DVBSx_tuner_LPF_100kHz_saddr_offset                            0x000001c6
+#define rc_DVBSx_blind_scan_start_freq_100kHz_saddr_offset                0x000001cc
+#define rc_DVBSx_blind_scan_min_sym_rate_kHz_saddr_offset                 0x000001d0
+#define rc_DVBSx_blind_scan_end_freq_100kHz_saddr_offset                  0x000001d2
+#define rc_DVBSx_blind_scan_channel_info_offset_saddr_offset              0x000001d4
+#define rc_DVBSx_blind_scan_max_sym_rate_kHz_saddr_offset                 0x000001d6
+#define rc_DVBSx_decode_mode_saddr_offset                                 0x00000204
+#define rc_DVBSx_iq_mode_saddr_offset                                     0x0000020a
+#define rc_DVBSx_dishpoint_mode_saddr_offset                              0x0000020e
+#define rc_DVBSx_blind_scan_reset_saddr_offset                            0x00000210
+#define rc_DVBSx_functional_mode_saddr_offset                             0x00000212
+#define rc_DVBSx_blind_scan_tuner_spectrum_inversion_saddr_offset         0x00000226
+#define rc_DVBSx_IF_Offset_10kHz_saddr_offset                             0x00000234
+#define rc_DVBSx_dvbs2_fec_coderate_caddr_offset                          0x0000023f
+#define rc_DVBSx_adc_Q_chan_sel_caddr_offset                              0x00000246
+#define rc_DVBSx_adc_I_chan_sel_caddr_offset                              0x00000247
+#define rc_DVBSx_dvbs2_code_rate_saddr_offset                             0x00000258
+#define rc_DVBSx_dvbs2_modulation_saddr_offset                            0x0000025a
+#define rc_DVBSx_int_adc_clk_MHz_saddr_offset                             0x000002a0
+
+#define rs_DVBSx_modulation_iaddr_offset                                  0x0000000c
+#define rs_DVBSx_pilot_iaddr_offset                                       0x00000010
+#define rs_DVBSx_int_SNR_dB_iaddr_offset                                  0x00000020
+#define rs_DVBSx_blind_scan_channel_count_saddr_offset                    0x000000b0
+#define rs_DVBSx_blind_scan_error_code_saddr_offset                       0x000000b4
+#define rs_DVBSx_blind_scan_progress_saddr_offset                         0x000000b6
+#define rs_DVBSx_post_viterbi_BER_estimate_x10M_iaddr_offset    		  0x000000c4
+#define rs_DVBSx_post_LDPC_BER_estimate_x10M_iaddr_offset                 0x000000c8
+#define rs_DVBSx_pre_LDPC_BER_estimate_x10M_iaddr_offset        		  0x000000cc
+#define rs_DVBSx_detected_alpha_iaddr_offset                              0x000000d0
+#define rs_DVBSx_int_carrier_freq_100kHz_saddr_offset                     0x00000078
+#define rs_DVBSx_fec_lock_saddr_offset                                    0x0000009e
+
+
+#define hw_diseqc_tx_cntrl_offset                                     0x0 
+#define hw_diseqc_tone_frac_n_offset                                  0x4 
+#define hw_diseqc_tone_frac_d_offset                                  0x8 
+#define hw_diseqc_tx_st_offset                                        0xC 
+#define hw_diseqc_rx_parity_offset                                    0x10
+#define hw_diseqc_rx_msg_tim_offset                                   0x14
+#define hw_diseqc_rx_st_offset                                        0x18
+#define hw_diseqc_rx_cntrl_offset                                     0x1C
+#define hw_diseqc_srst_offset                                         0x20
+#define hw_diseqc_samp_frac_n_offset                                  0x28
+#define hw_diseqc_samp_frac_d_offset                                  0x2C
+#define hw_rx_fifo_map_offset                                         0x40
+#define hw_tx_fifo_map_offset                                         0x80
+
+/// Represents the code rate. The Availink device can automatically detect the code rate of the input signal.
+typedef enum AVL_DVBS_CodeRate
+{
+    AVL_DVBS_CR_1_2  =   0, 
+    AVL_DVBS_CR_2_3  =   1,
+    AVL_DVBS_CR_3_4  =   2,
+    AVL_DVBS_CR_5_6  =   3,
+    AVL_DVBS_CR_6_7  =   4,
+    AVL_DVBS_CR_7_8  =   5
+}AVL_DVBS_CodeRate;
+
+
+typedef enum AVL_DVBS2_CodeRate
+{
+    AVL_DVBS2_CR_1_4     =   0,
+    AVL_DVBS2_CR_1_3     =   1,
+    AVL_DVBS2_CR_2_5     =   2,
+    AVL_DVBS2_CR_1_2     =   3,
+    AVL_DVBS2_CR_3_5     =   4,
+    AVL_DVBS2_CR_2_3     =   5,
+    AVL_DVBS2_CR_3_4     =   6,
+    AVL_DVBS2_CR_4_5     =   7,
+    AVL_DVBS2_CR_5_6     =   8,
+    AVL_DVBS2_CR_8_9     =   9,
+    AVL_DVBS2_CR_9_10    =   10
+}AVL_DVBS2_CodeRate;
+
+typedef enum AVL_DVBSx_Pilot
+{
+    AVL_DVBSx_Pilot_OFF  =   0,                  // Pilot off
+    AVL_DVBSx_Pilot_ON   =   1                   // Pilot on
+}AVL_DVBSx_Pilot;
+
+typedef enum AVL_DVBSx_ModulationMode
+{
+    AVL_DVBSx_QPSK   =   0,                      // QPSK
+    AVL_DVBSx_8PSK   =   1,                      // 8-PSK
+    AVL_DVBSx_16APSK =   2,                      // 16-APSK
+    AVL_DVBSx_32APSK =   3                       // 32-APSK
+}AVL_DVBSx_ModulationMode;
+
+
+typedef enum AVL_DVBSx_RollOff
+{
+    AVL_DVBSx_RollOff_20 = 0,                    // Roll off is 0.20
+    AVL_DVBSx_RollOff_25 = 1,                    // Roll off is 0.25
+    AVL_DVBSx_RollOff_35 = 2                     // Roll off is 0.35
+}AVL_DVBSx_RollOff;
+
+typedef enum AVL_DVBSx_Standard
+{
+    AVL_DVBS     =   0,                          // DVBS standard
+    AVL_DVBS2    =   1                           // DVBS2 standard
+}AVL_DVBSx_Standard;    
+
+// Defines the AVL device spectrum inversion mode
+typedef enum AVL_SpectrumInversion
+{
+    AVL_SPECTRUM_NORMAL     =   0,                      // Signal spectrum in normal.
+    AVL_SPECTRUM_INVERTED   =   1,                      // Signal spectrum in inverted.
+    AVL_SPECTRUM_AUTO       =   2                       // Signal spectrum isn't known.
+}AVL_SpectrumInversion;
+
+// Defines the ON/OFF options for the AVLEM61 device.
+typedef enum AVL_Switch
+{
+    AVL_ON  =   0,                              // switched on
+    AVL_OFF =   1                               // switched off
+}AVL_Switch;
+
+// Defines the device functional mode.
+typedef enum AVL_FunctionalMode
+{
+    AVL_FuncMode_Demod      =   0,              // The device is in demod mode.
+    AVL_FuncMode_BlindScan  =   1               // The device is in blind scan mode.
+}AVL_FunctionalMode;
+
+typedef enum AVL_Diseqc_TxGap
+{
+    AVL_DTXG_15ms = 0,                          // The gap is 15 ms.
+    AVL_DTXG_20ms = 1,                          // The gap is 20 ms.
+    AVL_DTXG_25ms = 2,                          // The gap is 25 ms.
+    AVL_DTXG_30ms = 3                           // The gap is 30 ms.
+}AVL_Diseqc_TxGap;
+
+typedef enum AVL_Diseqc_TxMode
+{
+    AVL_DTM_Modulation = 0,                     // Use modulation mode.
+    AVL_DTM_Tone0 = 1,                          // Send out tone 0.
+    AVL_DTM_Tone1 = 2,                          // Send out tone 1.
+    AVL_DTM_Continuous = 3                      // Continuously send out pulses.
+}AVL_Diseqc_TxMode;
+
+typedef enum AVL_Diseqc_RxTime
+{
+    AVL_DRT_150ms = 0,                          // Wait 150 ms for receive data and then close the input FIFO.
+    AVL_DRT_170ms = 1,                          // Wait 170 ms for receive data and then close the input FIFO.
+    AVL_DRT_190ms = 2,                          // Wait 190 ms for receive data and then close the input FIFO.
+    AVL_DRT_210ms = 3                           // Wait 210 ms for receive data and then close the input FIFO.
+}AVL_Diseqc_RxTime;
+
+// Stores blind scan info
+typedef struct AVL_BSInfo
+{
+    u16 m_uiProgress;                        // The percentage completion of the blind scan procedure. A value of 100 indicates that the blind scan is finished.
+    u16 m_uiChannelCount;                    // The number of channels detected thus far by the blind scan operation.  The Availink device can store up to 120 detected channels.
+    u16 m_uiNextStartFreq_100kHz;            // The start frequency of the next scan in units of 100kHz.
+    u16 m_uiResultCode;                      // The result of the blind scan operation.  Possible values are:  0 - blind scan operation normal; 1 -- more than 120 channels have been detected.
+}AVL_BSInfo;
+
+// Stores channel info
+typedef struct AVL_ChannelInfo
+{
+    u32 m_uiFrequency_kHz;                   // The channel carrier frequency in units of kHz. 
+    u32 m_uiSymbolRate_Hz;                   // The symbol rate in units of Hz. 
+    u32 m_Flags;                             // Contains bit-mapped fields which store additional channel configuration information.
+}AVL_ChannelInfo;
+
+typedef struct AVL_DVBSxModulationInfo
+{
+    AVL_DVBSx_ModulationMode    eDVBSxModulationMode;
+    AVL_DVBS_CodeRate           eDVBSCodeRate;
+    AVL_DVBS2_CodeRate          eDVBS2CodeRate;
+    AVL_DVBSx_Pilot             eDVBSxPilot;
+    AVL_DVBSx_RollOff           eDVBSxRollOff;
+    AVL_DVBSx_Standard          eDVBSxStandard;
+}AVL_DVBSxModulationInfo;
+
+typedef struct AVL_DVBSxManualLockInfo
+{
+    AVL_DVBSx_ModulationMode    eDVBSxModulationMode;
+    AVL_DVBS_CodeRate           eDVBSCodeRate;
+    AVL_DVBS2_CodeRate          eDVBS2CodeRate;
+    AVL_DVBSx_Pilot             eDVBSxPilot;
+    AVL_SpectrumInversion       eDVBSxSpecInversion;
+    AVL_DVBSx_Standard          eDVBSxStandard;
+    u32                  uiDVBSxSymbolRateSps;
+}AVL_DVBSxManualLockInfo;
+
+// Defines the device spectrum polarity setting. 
+typedef enum AVL_BlindSanSpectrumPolarity
+{
+    AVL_Spectrum_Invert = 0,
+    AVL_Spectrum_Normal = 1
+}AVL_BlindSanSpectrumPolarity;
+
+/// Stores the blind scan parameters which are passed to the blind scan function.
+typedef struct AVL_BlindScanPara
+{
+    u16 m_uiStartFreq_100kHz;                // The start scan frequency in units of 100kHz. The minimum value depends on the tuner specification. 
+    u16 m_uiStopFreq_100kHz;                 // The stop scan frequency in units of 100kHz. The maximum value depends on the tuner specification.
+    u16 m_uiMinSymRate_kHz;                  // The minimum symbol rate to be scanned in units of kHz. The minimum value is 1000 kHz.
+    u16 m_uiMaxSymRate_kHz;                  // The maximum symbol rate to be scanned in units of kHz. The maximum value is 45000 kHz.
+    AVL_BlindSanSpectrumPolarity m_enumBSSpectrumPolarity;
+}AVL_BlindScanPara;
+
+// Stores DiSEqC operation parameters
+typedef struct AVL_Diseqc_Para
+{
+    u16              uiToneFrequencyKHz;// The DiSEqC bus speed in units of kHz. Normally, it is 22kHz. 
+    AVL_Diseqc_TxGap        eTXGap;            // Transmit gap
+    AVL_Diseqc_WaveFormMode eTxWaveForm;       // Transmit waveform format
+    AVL_Diseqc_RxTime       eRxTimeout;        // Receive time frame window
+    AVL_Diseqc_WaveFormMode eRxWaveForm;       // Receive waveform format
+}AVL_Diseqc_Para;
+
+// Stores the DiSEqC transmitter status.
+typedef struct AVL_Diseqc_TxStatus
+{
+    u8   m_TxDone;                           // Indicates whether the transmission is complete (1 - transmission is finished, 0 - transmission is still in progress).
+    u8   m_TxFifoCount;                      // The number of bytes remaining in the transmit FIFO
+}AVL_Diseqc_TxStatus;
+
+// Stores the DiSEqC receiver status
+typedef struct AVL_Diseqc_RxStatus
+{
+    u8   m_RxFifoCount;                      // The number of bytes in the DiSEqC receive FIFO.
+    u8   m_RxFifoParChk;                     // The parity check result of the received data. This is a bit-mapped field in which each bit represents the parity check result for each each byte in the receive FIFO.  The upper bits without corresponding data are undefined. If a bit is 1, the corresponding byte in the FIFO has good parity. For example, if three bytes are in the FIFO, and the parity check value is 0x03 (value of bit 2 is zero), then the first and the second bytes in the receive FIFO are good. The third byte had bad parity. 
+    u8   m_RxDone;                           // 1 if the receiver window is turned off, 0 if it is still in receiving state.
+}AVL_Diseqc_RxStatus;
+
+
+
+
+
+
+/* DVBC */
+//DVBC config registers offset address
+#define rc_DVBC_symbol_rate_Hz_iaddr_offset                     0x00000000
+#define rc_DVBC_sample_rate_Hz_iaddr_offset                     0x00000004
+#define rc_DVBC_dmd_clk_Hz_iaddr_offset                         0x00000008
+#define rc_DVBC_j83b_mode_caddr_offset                          0x00000017
+#define rc_DVBC_tuner_type_caddr_offset                         0x00000024
+#define rc_DVBC_input_format_caddr_offset                       0x00000025
+#define rc_DVBC_spectrum_invert_caddr_offset                    0x00000026
+#define rc_DVBC_input_select_caddr_offset                       0x00000027
+#define rc_DVBC_if_freq_Hz_iaddr_offset                         0x00000028
+#define rc_DVBC_qam_mode_iaddr_offset                           0x0000002c
+#define rc_DVBC_rfagc_pol_caddr_offset						    0x00000049
+#define rc_DVBC_fec_clk_Hz_iaddr_offset                         0x00000050
+#define rc_DVBC_get_btr_crl_iaddr_offset                        0x00000080
+#define rc_DVBC_qam_mode_scan_control_iaddr_offset              0x00000090
+#define rc_DVBC_adc_sel_caddr_offset							0x000001ef
+#define rc_DVBC_adc_use_pll_clk_caddr_offset				    0x000001ee
+
+
+
+//DVBC status registers offset address
+#define rs_DVBC_mode_status_iaddr_offset                        0x00000004
+#define rs_DVBC_snr_dB_x100_saddr_offset                        0x0000000e
+#define rs_DVBC_j83b_il_mode_caddr_offset                       0x0000001d
+#define rs_DVBC_post_viterbi_BER_estimate_x10M_iaddr_offset     0x0000004c
+
+typedef enum AVL_DVBC_TunerType
+{
+    AVL_DVBC_IF          =       0,
+    AVL_DVBC_BASEBAND    =       1
+}AVL_DVBC_TunerType;
+
+typedef enum AVL_DVBC_ChannelType
+{
+    AVL_DVBC_I_CHANNEL   =       0,
+    AVL_DVBC_Q_CHANNEL   =       1
+}AVL_DVBC_ChannelType;
+
+typedef enum AVL_DVBCQAMMode
+{
+    AVL_DVBC_16QAM               =   0,      
+    AVL_DVBC_32QAM               =   1,
+    AVL_DVBC_64QAM               =   2,      
+    AVL_DVBC_128QAM              =   3,
+    AVL_DVBC_256QAM              =   4
+}AVL_DVBCQAMMode;
+
+// Defines the symbol interleave mode of the received DVBC signal, only used for J.83B.
+typedef enum AVL_DVBCInterleaveMode
+{
+    AVL_DVBC_INTERLEAVE_128_1_0  =   0,
+    AVL_DVBC_INTERLEAVE_128_1_1  =   1,
+    AVL_DVBC_INTERLEAVE_128_2    =   2,
+    AVL_DVBC_INTERLEAVE_64_2     =   3,
+    AVL_DVBC_INTERLEAVE_128_3    =   4,
+    AVL_DVBC_INTERLEAVE_32_4     =   5,
+    AVL_DVBC_INTERLEAVE_128_4    =   6,
+    AVL_DVBC_INTERLEAVE_16_8     =   7,
+    AVL_DVBC_INTERLEAVE_128_5    =   8,
+    AVL_DVBC_INTERLEAVE_8_16     =   9,
+    AVL_DVBC_INTERLEAVE_128_6    =   10,
+    AVL_DVBC_INTERLEAVE_128_7    =   12,
+    AVL_DVBC_INTERLEAVE_128_8    =   14
+}AVL_DVBCInterleaveMode;
+
+
+typedef struct AVL_DVBCModulationInfo
+{
+	AVL_DVBCQAMMode         eQAMMode;
+	AVL_DVBCInterleaveMode  eInterleaveMode;
+}AVL_DVBCModulationInfo;
+ 
+ typedef struct AVL_DVBC_SQI_CN_Table_Element
+ {
+	 AVL_DVBC_Standard eStandard;
+	 AVL_DVBCQAMMode modulation;
+	 u32 CN_Test_Result_x100_db;
+ }AVL_DVBC_SQI_CN_Table_Element;
+
+
+/* DVBT2 */
+
+#define rc_DVBTx_fund_rate_Hz_iaddr_offset                       0x00000004
+#define rc_DVBTx_sample_rate_Hz_iaddr_offset                     0x00000008
+#define rc_DVBTx_rf_agc_pol_caddr_offset                         0x0000000f
+#define rc_DVBTx_tuner_type_caddr_offset                         0x00000040
+#define rc_DVBTx_input_format_caddr_offset                       0x00000041
+#define rc_DVBTx_spectrum_invert_caddr_offset                    0x00000042
+#define rc_DVBTx_input_select_caddr_offset                       0x00000043
+#define rc_DVBTx_nom_carrier_freq_Hz_iaddr_offset                0x00000044
+#define rc_DVBTx_l1_proc_only_caddr_offset                       0x00000054
+#define rc_DVBTx_common_PLP_present_caddr_offset                 0x00000055
+#define rc_DVBTx_common_PLP_ID_caddr_offset                      0x00000056
+#define rc_DVBTx_data_PLP_ID_caddr_offset                        0x00000057
+#define rc_DVBTx_dvbt_layer_select_caddr_offset                  0x0000006a
+#define rc_DVBTx_acquire_mode_caddr_offset                       0x0000006b
+#define rc_DVBTx_mpeg_clk_rate_Hz_iaddr_offset                   0x0000006c
+#define rc_DVBTx_adc_sel_caddr_offset							 0x00000077
+#define rc_DVBTx_adc_use_pll_clk_caddr_offset                    0x00000076
+
+
+#define rs_DVBTx_rx_mode_caddr_offset                            0x000000d0
+#define rs_DVBTx_fec_lock_caddr_offset                           0x000000d2
+#define rs_DVBTx_snr_dB_x100_saddr_offset                        0x000000d6
+#define rs_DVBTx_post_viterbi_BER_estimate_x10M_iaddr_offset     0x00000114
+#define rs_DVBTx_post_LDPC_BER_estimate_x1B_iaddr_offset         0x00000118
+#define rs_DVBTx_pre_LDPC_BER_estimate_x10M_iaddr_offset         0x0000011c
+#define rs_DVBTx_plp_list_request_caddr_offset                   0x00000133
+
+#define rs_DVBTx_data_PLP_ID_caddr_offset                   0x00000000
+#define rs_DVBTx_data_PLP_TYPE_caddr_offset                 0x00000001
+#define rs_DVBTx_data_PLP_COD_caddr_offset                  0x00000007
+#define rs_DVBTx_data_PLP_MOD_caddr_offset                  0x00000008
+#define rs_DVBTx_data_PLP_ROTATION_caddr_offset             0x00000009
+#define rs_DVBTx_data_PLP_FEC_TYPE_caddr_offset             0x0000000b
+
+#define rs_DVBTx_common_PLP_ID_caddr_offset                 0x00000000
+#define rs_DVBTx_common_PLP_COD_caddr_offset                0x00000007
+#define rs_DVBTx_common_PLP_MOD_caddr_offset                0x00000008
+#define rs_DVBTx_common_PLP_ROTATION_caddr_offset           0x00000009
+#define rs_DVBTx_common_PLP_FEC_TYPE_caddr_offset           0x0000000b
+
+#define rs_DVBTx_P1_S2_field_2_caddr_offset                 0x00000003
+#define rs_DVBTx_MISO_SISO_caddr_offset                     0x00000005
+#define rs_DVBTx_T2_profile_caddr_offset                    0x00000006
+#define rs_DVBTx_FFT_size_caddr_offset                      0x00000007
+
+#define rs_DVBTx_NUM_PLP_caddr_offset                       0x00000002
+
+#define rs_DVBTx_constellation_caddr_offset                 0x00000001
+#define rs_DVBTx_hierarchy_caddr_offset                     0x00000002
+#define rs_DVBTx_HP_code_rate_caddr_offset                  0x00000003
+#define rs_DVBTx_LP_code_rate_caddr_offset                  0x00000004
+#define rs_DVBTx_guard_interval_caddr_offset                0x00000005
+#define rs_DVBTx_transmission_mode_caddr_offset             0x00000006
+
+#define rs_DVBTx_BWT_EXT_caddr_offset                0x00000001
+#define rs_DVBTx_GUARD_INTERVAL_caddr_offset         0x00000005
+#define rs_DVBTx_PAPR_caddr_offset                   0x00000006
+#define rs_DVBTx_L1_MOD_caddr_offset                 0x00000007
+#define rs_DVBTx_PILOT_PATTERN_caddr_offset          0x00000014
+#define rs_DVBTx_CELL_ID_saddr_offset                0x00000016
+#define rs_DVBTx_NETWORK_ID_saddr_offset             0x00000018
+#define rs_DVBTx_T2_SYSTEM_ID_saddr_offset           0x0000001a
+#define rs_DVBTx_NUM_T2_FRAMES_caddr_offset          0x0000001d
+#define rs_DVBTx_NUM_DATA_SYMBOLS_saddr_offset       0x0000001e
+
+#define rs_DVBTx_Signal_Presence_iaddr_offset        0x00000150
+
+typedef enum AVL_DVBTx_TunerType
+{
+    AVL_DVBTX_REAL_IF            =   0,
+    AVL_DVBTX_COMPLEX_BASEBAND   =   1,
+    AVL_DVBTX_REAL_IF_FROM_Q     =   2
+}AVL_DVBTx_TunerType;
+
+typedef enum AVL_DVBT2_PLP_Type
+{
+    AVL_DVBT2_SINGLE_PLP         =   0,
+    AVL_DVBT2_MULTIPLE_PLP       =   1
+}AVL_DVBT2_PLP_Type;
+
+typedef enum AVL_DVBTxBandWidth
+{
+    AVL_DVBTx_BW_1M7 =   0,
+    AVL_DVBTx_BW_5M  =   1,
+    AVL_DVBTx_BW_6M  =   2,
+    AVL_DVBTx_BW_7M  =   3,
+    AVL_DVBTx_BW_8M  =   4
+}AVL_DVBTxBandWidth;
+
+typedef enum AVL_DVBTx_LockMode
+{
+    AVL_DVBTx_LockMode_T2BASE_T   =   0,
+    AVL_DVBTx_LockMode_T2LITE_T   =   1,
+    AVL_DVBTx_LockMode_T2BASE     =   2,
+    AVL_DVBTx_LockMode_T2LITE     =   3,
+    AVL_DVBTx_LockMode_T_ONLY     =   4,
+	AVL_DVBTx_LockMode_ALL        =   5
+}AVL_DVBTx_LockMode;
+
+typedef enum AVL_DVBT_Layer
+{
+    AVL_DVBT_LAYER_LP    =   0,
+    AVL_DVBT_LAYER_HP    =   1
+}AVL_DVBT_Layer;
+
+typedef enum AVL_DVBT_FFTSize
+{
+    AVL_DVBT_FFT_2K      =   0, 
+    AVL_DVBT_FFT_8K      =   1,
+    AVL_DVBT_FFT_UNKNOWN =   2
+}AVL_DVBT_FFTSize;
+
+typedef enum AVL_DVBT_GuardInterval
+{
+    AVL_DVBT_GUARD_1_32  =   0,
+    AVL_DVBT_GUARD_1_16  =   1,
+    AVL_DVBT_GUARD_1_8   =   2,
+    AVL_DVBT_GUARD_1_4   =   3
+}AVL_DVBT_GuardInterval;
+
+typedef enum AVL_DVBT_ModulationMode
+{
+    AVL_DVBT_QPSK            =   0,
+    AVL_DVBT_16QAM           =   1,
+    AVL_DVBT_64QAM           =   2,
+    AVL_DVBT_MOD_UNKNOWN     =   3
+}AVL_DVBT_ModulationMode;
+
+typedef enum AVL_DVBT_Hierarchy
+{
+    AVL_DVBT_HIER_NONE       =   0,
+    AVL_DVBT_HIER_ALPHA_1    =   1,
+    AVL_DVBT_HIER_ALPHA_2    =   2,
+    AVL_DVBT_HIER_ALPHA_4    =   3
+}AVL_DVBT_Hierarchy;
+
+typedef enum AVL_DVBT_CodeRate
+{
+    AVL_DVBT_CR_1_2  =   0,
+    AVL_DVBT_CR_2_3  =   1,
+    AVL_DVBT_CR_3_4  =   2,
+    AVL_DVBT_CR_5_6  =   3,
+    AVL_DVBT_CR_7_8  =   4
+}AVL_DVBT_CodeRate;
+
+typedef enum AVL_DVBT2_FFTSize
+{
+    AVL_DVBT2_FFT_1K     =   0,
+    AVL_DVBT2_FFT_2K     =   1,
+    AVL_DVBT2_FFT_4K     =   2,
+    AVL_DVBT2_FFT_8K     =   3,
+    AVL_DVBT2_FFT_16K    =   4,
+    AVL_DVBT2_FFT_32K    =   5
+}AVL_DVBT2_FFTSize;
+
+typedef enum AVL_DVBT2_MISO_SISO
+{
+    AVL_DVBT2_SISO   =   0,
+    AVL_DVBT2_MISO   =   1
+}AVL_DVBT2_MISO_SISO;
+
+
+typedef enum AVL_DVBT2_PROFILE
+{
+    AVL_DVBT2_PROFILE_BASE    =  0,
+    AVL_DVBT2_PROFILE_LITE    =  1,
+    AVL_DVBT2_PROFILE_UNKNOWN =  2
+}AVL_DVBT2_PROFILE;
+
+typedef enum AVL_DVBT2_PILOT_PATTERN
+{
+    AVL_DVBT2_PP_PP1           = 0,
+    AVL_DVBT2_PP_PP2           = 1,
+    AVL_DVBT2_PP_PP3           = 2,
+    AVL_DVBT2_PP_PP4           = 3,
+    AVL_DVBT2_PP_PP5           = 4,
+    AVL_DVBT2_PP_PP6           = 5,
+    AVL_DVBT2_PP_PP7           = 6,
+    AVL_DVBT2_PP_PP8           = 7,
+    AVL_DVBT2_PP_DVBT          = 8,
+    AVL_DVBT2_PP_DVBT_REVERSE  = 9,
+    AVL_DVBT2_PP_UNKNOWN       = 10
+}AVL_DVBT2_PILOT_PATTERN;
+
+typedef enum AVL_DVBT2_DATA_PLP_TYPE
+{
+    AVL_DVBT2_DATA_PLP_TYPE1 =   1,
+    AVL_DVBT2_DATA_PLP_TYPE2 =   2
+}AVL_DVBT2_DATA_PLP_TYPE;
+
+typedef enum AVL_DVBT2_CodeRate
+{
+    AVL_DVBT2_CR_1_2 = 0,
+    AVL_DVBT2_CR_3_5 = 1,
+    AVL_DVBT2_CR_2_3 = 2,
+    AVL_DVBT2_CR_3_4 = 3,
+    AVL_DVBT2_CR_4_5 = 4,
+    AVL_DVBT2_CR_5_6 = 5,
+    AVL_DVBT2_CR_1_3 = 6,
+    AVL_DVBT2_CR_2_5 = 7
+}AVL_DVBT2_CodeRate;
+
+typedef enum AVL_DVBT2_PLP_ModulationMode
+{
+    AVL_DVBT2_QPSK   = 0,
+    AVL_DVBT2_16QAM  = 1,
+    AVL_DVBT2_64QAM  = 2, 
+    AVL_DVBT2_256QAM = 3
+}AVL_DVBT2_PLP_ModulationMode;
+
+typedef enum AVL_DVBT2_L1_Modulation
+{
+    AVL_DVBT2_L1_BPSK = 0,
+    AVL_DVBT2_L1_QPSK = 1,
+	AVL_DVBT2_L1_16QAM = 2,
+	AVL_DVBT2_L1_64QAM = 3
+}AVL_DVBT2_L1_Modulation;
+
+typedef enum AVL_DVBT2_PLP_Constellation_Rotation
+{
+    AVL_DVBT2_PLP_NOT_ROTATION   =   0,
+    AVL_DVBT2_PLP_ROTATION       =   1
+}AVL_DVBT2_PLP_Constellation_Rotation;
+
+typedef enum AVL_DVBT2_PLP_FEC_Type
+{
+    AVL_DVBT2_FEC_LDPC16K    =   0,
+    AVL_DVBT2_FEC_LDPC64K    =   1
+}AVL_DVBT2_PLP_FEC_Type;
+
+typedef enum AVL_DVBTx_Standard
+{
+    AVL_DVBTx_Standard_T     =   0,                  //the DVB-T standard
+    AVL_DVBTx_Standard_T2    =   1                   //the DVB-T2 standard
+}AVL_DVBTx_Standard;    
+
+typedef enum AVL_DVBT2_PAPR
+{
+    AVL_DVBT2_PAPR_NONE       =     0,
+    AVL_DVBT2_PAPR_ACE        =     1,
+    AVL_DVBT2_PAPR_TR         =     2,
+    AVL_DVBT2_PAPR_BOTH       =     3
+}AVL_DVBT2_PAPR;
+
+typedef enum AVL_DVBT2_GUARD_INTERVAL
+{
+    AVL_DVBT2_GI_1_32         =     0,
+    AVL_DVBT2_GI_1_16         =     1,
+    AVL_DVBT2_GI_1_8          =     2,
+    AVL_DVBT2_GI_1_4          =     3,
+    AVL_DVBT2_GI_1_128        =     4,
+    AVL_DVBT2_GI_19_128       =     5,
+    AVL_DVBT2_GI_19_256       =     6
+}AVL_DVBT2_GUARD_INTERVAL;
+
+
+
+typedef struct AVL_DVBT_RF_Table_Element
+{
+    AVL_DVBT_ModulationMode modulation;
+    AVL_DVBT_CodeRate code_rate;
+    AVL_int32 Nordig_RF_Ref_dbm;
+}AVL_DVBT_RF_Table_Element;
+
+typedef struct AVL_DVBT_BERSQI_List
+{
+    u32                 m_ber;
+    u32                 m_ber_sqi;
+}AVL_DVBT_BERSQI_List;
+
+typedef struct AVL_DVBT_Non_Hierarchical_CN_Table_Element
+{
+    AVL_DVBT_ModulationMode modulation;
+    AVL_DVBT_CodeRate hp_code_rate;
+    AVL_int32 CN_NordigP1_x100_db;
+}AVL_DVBT_Non_Hierarchical_CN_Table_Element;
+
+typedef struct AVL_DVBT_Hierarchical_CN_Table_Element
+{
+    AVL_DVBT_Layer selected_layer;
+    AVL_DVBT_ModulationMode modulation;
+    AVL_DVBT_CodeRate code_rate;
+    AVL_DVBT_Hierarchy hierarchy;
+    AVL_int32 CN_NordigP1_x100_db;
+}AVL_DVBT_Hierarchical_CN_Table_Element;
+
+typedef struct DVBT2_CN_Table_Element
+{
+    AVL_DVBT2_PLP_ModulationMode modulation;
+    AVL_DVBT2_CodeRate code_rate;
+    AVL_int32 CN_NordigP1_x100_db;
+}DVBT2_CN_Table_Element;
+
+// DVBT2 pilot boosting correct CN table
+typedef struct DVBT2_PBC_CN_Table_Element
+{
+    AVL_DVBT2_FFTSize fft_size;
+    AVL_DVBT2_PILOT_PATTERN pilot_pattern;
+    AVL_int32 PCB_CN;
+}DVBT2_PBC_CN_Table_Element;
+typedef struct AVL_DVBT2_RF_Table_Element
+{
+    AVL_DVBT2_PLP_ModulationMode modulation;
+    AVL_DVBT2_CodeRate code_rate;
+    AVL_int32 Nordig_RF_Ref_dbm;
+}AVL_DVBT2_RF_Table_Element;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+AVL_DVBC_SQI_CN_Table_Element AVL_DVBC_CN_Table[]=
+{
+    //profile 1, AWGN
+    {AVL_DVBC_J83A, AVL_DVBC_16QAM  , 1700}, 
+    {AVL_DVBC_J83A, AVL_DVBC_32QAM  , 1980},
+    {AVL_DVBC_J83A, AVL_DVBC_64QAM  , 2300}, 
+    {AVL_DVBC_J83A, AVL_DVBC_128QAM , 2600}, 
+    {AVL_DVBC_J83A, AVL_DVBC_256QAM , 2920},
+    
+    {AVL_DVBC_J83B, AVL_DVBC_64QAM ,  2180},
+    {AVL_DVBC_J83B, AVL_DVBC_256QAM , 2810}
+};
+
+AVL_DVBT_Non_Hierarchical_CN_Table_Element AVL_DVBT_Non_Hierarchical_CN_Table[]=
+{
+    //profile 1, Gaussian
+    {AVL_DVBT_QPSK, AVL_DVBT_CR_1_2, 510},
+    {AVL_DVBT_QPSK, AVL_DVBT_CR_2_3, 690},
+    {AVL_DVBT_QPSK, AVL_DVBT_CR_3_4, 790},
+    {AVL_DVBT_QPSK, AVL_DVBT_CR_5_6, 890},
+    {AVL_DVBT_QPSK, AVL_DVBT_CR_7_8, 970},
+
+    {AVL_DVBT_16QAM, AVL_DVBT_CR_1_2, 1080},
+    {AVL_DVBT_16QAM, AVL_DVBT_CR_2_3, 1310},
+    {AVL_DVBT_16QAM, AVL_DVBT_CR_3_4, 1460},
+    {AVL_DVBT_16QAM, AVL_DVBT_CR_5_6, 1560},
+    {AVL_DVBT_16QAM, AVL_DVBT_CR_7_8, 1600},
+
+    {AVL_DVBT_64QAM, AVL_DVBT_CR_1_2, 1650},
+    {AVL_DVBT_64QAM, AVL_DVBT_CR_2_3, 1870},
+    {AVL_DVBT_64QAM, AVL_DVBT_CR_3_4, 2020},
+    {AVL_DVBT_64QAM, AVL_DVBT_CR_5_6, 2160},
+    {AVL_DVBT_64QAM, AVL_DVBT_CR_7_8, 2250}
+};
+
+
+
+AVL_DVBT_Hierarchical_CN_Table_Element AVL_DVBT_Hierarchical_CN_Table[]=
+{
+    //profile 1, Gaussian
+    //For HP, only QPSK is used
+
+    //64QAM
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_64QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_1,1090},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_64QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_1,1670},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_64QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_1,1410},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_64QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_1,1910},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_64QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_1,1570},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_64QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_1,2090},
+
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_64QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_2,850},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_64QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_2,1850},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_64QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_2,1100},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_64QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_2,2120},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_64QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_2,1280},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_64QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_2,2360},
+
+    //16QAM
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_16QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_2,680},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_16QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_2,1500},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_16QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_2,910},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_16QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_2,1720},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_16QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_2,1040},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_16QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_2,1840},
+
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_16QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_4,580},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_16QAM, AVL_DVBT_CR_1_2,AVL_DVBT_HIER_ALPHA_4,1950},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_16QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_4,790},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_16QAM, AVL_DVBT_CR_2_3,AVL_DVBT_HIER_ALPHA_4,2140},
+
+    {AVL_DVBT_LAYER_HP, AVL_DVBT_16QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_4,910},
+    {AVL_DVBT_LAYER_LP, AVL_DVBT_16QAM, AVL_DVBT_CR_3_4,AVL_DVBT_HIER_ALPHA_4,2250}
+};
+
+
+DVBT2_CN_Table_Element DVBT2_RAW_CN_Table[]=
+{
+    //profile 1, Gaussian
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_1_3, -120}, //from DVB-S2 std
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_2_5, -030}, //from DVB-S2 std
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_1_2, 100},
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_3_5, 220},
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_2_3, 310},
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_3_4, 410},
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_4_5, 470},
+    {AVL_DVBT2_QPSK, AVL_DVBT2_CR_5_6, 520},
+
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_1_3, 370},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_2_5, 490},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_1_2, 620},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_3_5, 760},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_2_3, 890},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_3_4, 1000},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_4_5, 1080},
+    {AVL_DVBT2_16QAM, AVL_DVBT2_CR_5_6, 1130},
+
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_1_3, 760},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_2_5, 920},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_1_2, 1050},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_3_5, 1230},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_2_3, 1360},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_3_4, 1510},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_4_5, 1610},
+    {AVL_DVBT2_64QAM, AVL_DVBT2_CR_5_6, 1670},
+
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_1_3, 1110},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_2_5, 1290},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_1_2, 1440},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_3_5, 1670},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_2_3, 1810},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_3_4, 2000},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_4_5, 2130},
+    {AVL_DVBT2_256QAM, AVL_DVBT2_CR_5_6, 2200}
+};
+
+
+DVBT2_PBC_CN_Table_Element DVBT2_PCB_CN_Table[]=
+{
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP1, 34},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP2, 32},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP3, 44},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP4, 42},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP5, 48},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP6, 0},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP7, 29},
+    {AVL_DVBT2_FFT_1K, AVL_DVBT2_PP_PP8, 0},
+
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP1, 35},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP2, 33},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP3, 43},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP4, 42},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP5, 47},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP6, 0},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP7, 29},
+    {AVL_DVBT2_FFT_2K, AVL_DVBT2_PP_PP8, 0},
+
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP1, 39},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP2, 37},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP3, 47},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP4, 45},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP5, 51},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP6, 0},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP7, 34},
+    {AVL_DVBT2_FFT_4K, AVL_DVBT2_PP_PP8, 0},
+
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP1, 41},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP2, 39},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP3, 49},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP4, 48},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP5, 53},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP6, 0},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP7, 37},
+    {AVL_DVBT2_FFT_8K, AVL_DVBT2_PP_PP8, 37},
+
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP1, 41},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP2, 38},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP3, 49},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP4, 47},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP5, 52},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP6, 49},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP7, 33},
+    {AVL_DVBT2_FFT_16K, AVL_DVBT2_PP_PP8, 35},
+
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP1, 0},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP2, 37},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP3, 48},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP4, 45},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP5, 0},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP6, 48},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP7, 33},
+    {AVL_DVBT2_FFT_32K, AVL_DVBT2_PP_PP8, 35},
+};
+
+AVL_DVBT_BERSQI_List DVBT_BERSQI_Table[]=
+{
+    {100       ,    40  },
+    {178       ,    45  },
+    {316       ,    50  },
+    {562       ,    55  },
+    {1000      ,    60  },
+    {1000      ,    60  },
+    {1778      ,    65  },
+    {3162      ,    70  },
+    {5623      ,    75  },
+    {10000     ,    80  },
+    {17783     ,    85  },
+    {31623     ,    90  },
+    {56234     ,    95  },
+    {100000    ,    100 },
+    {177828    ,    105 },
+    {316228    ,    110 },
+    {562341    ,    115 },
+    {1000000   ,    120 },
+    {1778279   ,    125 },
+    {3162278   ,    130 },
+    {5623413   ,    135 },
+    {10000000  ,    140 }
+};
+
+
+
+AVL_DVBT_RF_Table_Element AVL_DVBT_RF_TABLE[]=
+{
+    {AVL_DVBT_QPSK,AVL_DVBT_CR_1_2,-93},
+    {AVL_DVBT_QPSK,AVL_DVBT_CR_2_3,-91},
+    {AVL_DVBT_QPSK,AVL_DVBT_CR_3_4,-90},
+    {AVL_DVBT_QPSK,AVL_DVBT_CR_5_6,-89},
+    {AVL_DVBT_QPSK,AVL_DVBT_CR_7_8,-88},
+
+    {AVL_DVBT_16QAM,AVL_DVBT_CR_1_2,-87},
+    {AVL_DVBT_16QAM,AVL_DVBT_CR_2_3,-85},
+    {AVL_DVBT_16QAM,AVL_DVBT_CR_3_4,-84},
+    {AVL_DVBT_16QAM,AVL_DVBT_CR_5_6,-83},
+    {AVL_DVBT_16QAM,AVL_DVBT_CR_7_8,-82},
+
+    {AVL_DVBT_64QAM,AVL_DVBT_CR_1_2,-82},
+    {AVL_DVBT_64QAM,AVL_DVBT_CR_2_3,-80},
+    {AVL_DVBT_64QAM,AVL_DVBT_CR_3_4,-78},
+    {AVL_DVBT_64QAM,AVL_DVBT_CR_5_6,-77},
+    {AVL_DVBT_64QAM,AVL_DVBT_CR_7_8,-76}
+};
+
+AVL_DVBT2_RF_Table_Element AVL_DVBT2_RF_TABLE[]=
+{
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_1_3,-101},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_2_5,-100},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_1_2,-96},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_3_5,-95},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_2_3,-94},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_3_4,-93},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_4_5,-92},
+    {AVL_DVBT2_QPSK,AVL_DVBT2_CR_5_6,-92},
+
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_1_3,-96},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_2_5,-95},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_1_2,-91},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_3_5,-89},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_2_3,-88},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_3_4,-87},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_4_5,-86},
+    {AVL_DVBT2_16QAM,AVL_DVBT2_CR_5_6,-86},
+
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_1_3,-93},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_2_5,-92},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_1_2,-86},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_3_5,-85},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_2_3,-83},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_3_4,-82},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_4_5,-81},
+    {AVL_DVBT2_64QAM,AVL_DVBT2_CR_5_6,-80},
+
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_1_3,-89},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_2_5,-88},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_1_2,-82},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_3_5,-80},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_2_3,-78},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_3_4,-76},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_4_5,-75},
+    {AVL_DVBT2_256QAM,AVL_DVBT2_CR_5_6,-74}
+};
+
+
+
+
+
+#endif
+
diff -rpuN a/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBCFw_.h b/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBCFw_.h
--- a/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBCFw_.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBCFw_.h	2016-04-09 10:31:21.232008195 -0300
@@ -0,0 +1,2284 @@
+/*
+ *           Copyright 2007-2014 Availink, Inc.
+ *
+ *  This software contains Availink proprietary information and
+ *  its use and disclosure are restricted solely to the terms in
+ *  the corresponding written license agreement. It shall not be 
+ *  disclosed to anyone other than valid licensees without
+ *  written permission of Availink, Inc.
+ *
+ */
+
+
+
+
+u8 AVL_Demod_Patch_DVBCFw [] = 
+{
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+0x58, 0x5E, 0xAE, 0xB0, 0x00, 0x00, 0x00, 0x00
+};
diff -rpuN a/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBSxFw_.h b/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBSxFw_.h
--- a/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBSxFw_.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBSxFw_.h	2016-04-09 10:31:21.236008180 -0300
@@ -0,0 +1,1875 @@
+/*
+ *           Copyright 2007-2014 Availink, Inc.
+ *
+ *  This software contains Availink proprietary information and
+ *  its use and disclosure are restricted solely to the terms in
+ *  the corresponding written license agreement. It shall not be 
+ *  disclosed to anyone other than valid licensees without
+ *  written permission of Availink, Inc.
+ *
+ */
+
+
+unsigned char AVL_Demod_Patch_DVBSxFw [] = 
+{
+0x12, 0x00, 0x01, 0x01, 0x00, 0x00, 0x1D, 0x0E, 0x00, 0x00, 0x00, 0x01, 0x00, 0x26, 0x00, 0x00, 
+0x00, 0x00, 0x01, 0x2A, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4D, 0x7A, 
+0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
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+0xF9, 0xB6, 0xFD, 0xBC, 0x39, 0xEF, 0x75, 0xEA, 0x1C, 0x48, 0xF3, 0xEF, 0x2E, 0x1D, 0xD4, 0x6A, 
+0xFB, 0xE8, 0xA1, 0x96, 0xEF, 0x09, 0x24, 0x6D, 0x1C, 0x2C, 0xE7, 0xBF, 0x74, 0xAF, 0xEB, 0xD3, 
+0xE1, 0x89, 0xD9, 0x6F, 0x0D, 0x99, 0x71, 0xFA, 0xD1, 0x98, 0x76, 0x99, 0x63, 0x47, 0x96, 0x44, 
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+0x7D, 0x2A, 0xE9, 0x61, 0x4D, 0x6A, 0xF6, 0xD7, 0x3F, 0x2A, 0xED, 0x1D, 0xA7, 0xA9, 0x58, 0x0C, 
+0xFE, 0x3E, 0xF4, 0xFF, 0x9C, 0x3C, 0xB2, 0xA8
+};
diff -rpuN a/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBTxFw_.h b/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBTxFw_.h
--- a/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBTxFw_.h	1969-12-31 21:00:00.000000000 -0300
+++ b/drivers/media/dvb/frontends/AVL_Demod_Patch_DVBTxFw_.h	2016-04-09 10:31:21.240008090 -0300
@@ -0,0 +1,2703 @@
+/*
+ *           Copyright 2007-2014 Availink, Inc.
+ *
+ *  This software contains Availink proprietary information and
+ *  its use and disclosure are restricted solely to the terms in
+ *  the corresponding written license agreement. It shall not be 
+ *  disclosed to anyone other than valid licensees without
+ *  written permission of Availink, Inc.
+ *
+ */
+
+
+
+
+u8 AVL_Demod_Patch_DVBTxFw [] = 
+{
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